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2006 data sheet description the pd6p8, 6p8a, 6p8b are microcontrollers for infrared remote control transmitters and are provided with a one-time prom as the program memory. because users can write programs for the pd6p8, 6p8a, 6p8b, they are ideal for program evaluation and small- scale production of application systems that use the pd67a, 67b, 68a, 68b. when reading this document, also refer to the following documents. pd67, 67a, 68, 68a, 69 data sheet: u14935e pd67b, 68b data sheet: u16792e features program memory (one-time prom): 2026 10 bits data memory (ram): 32 4 bits on-chip carrier generator for infrared remote control: the high-level and low-level width can be set separately from 250 ns to 64 s (@ f x = 4 mhz operation) via modulo registers 9-bit programmable timer: 1 channel instruction execution time: 16 s (@ f x = 4 mhz) stack level: 1 level (stack ram is for data memory rf as well) i/o pins (k i/o ): 8 units input pins (k i ): 4 units sense input pins (s 0 , s 2 ): 2 units ? 1 /led pin (i/o): 1 unit (when in output mode, this is the remote control transmission display pin) power supply voltage: v dd = 1.9 to 3.6 v operating ambient temperature: t a = ?0 to +85 c oscillator frequency: f x = 3.5 to 4.5 mhz on-chip poc circuit and ram retention detector on-chip oscillator ( pd6p8b) applications infrared remote control transmitters (for av and household electric appliances) 4-bit single-chip microcontroller for infrared remote control transmission mos integrated circuit pd6p8, 6p8a, 6p8b the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. the mark shows major revised points. document no. u17848ej3v0ds00 (3rd edition) date published december 2007 n printed in japan
2 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds ordering information part number package pd6p8mc-5a4-a 20-pin plastic ssop (7.62 mm (300)) pD6P8Amc-5a4-a 20-pin plastic ssop (7.62 mm (300)) pd6p8bmc-5a4-a note 20-pin plastic ssop (7.62 mm (300)) note under development remark products that have the part numbers suffixed by ?a?are lead-free products. pd6p8 pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) (1) normal operation mode (2) prom programming mode caution the item in parentheses indicates the processing of pins not used in the prom programming mode. l: connect each of these pins to gnd via a pull-down resistor. 1 2 3 4 5 6 7 8 9 10 k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 20 19 18 17 16 15 14 13 12 11 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 d 6 d 7 clk v dd x out x in gnd v pp d 5 d 4 d 3 d 2 d 1 d 0 md 3 md 2 md 1 md 0 (l)
3 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds pD6P8A pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) (1) normal operation mode (2) prom programming mode caution the item in parentheses indicates the processing of pins not used in the prom programming mode. f: these pins are pulled down internally, so leave them open. 1 2 3 4 5 6 7 8 9 10 k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 20 19 18 17 16 15 14 13 12 11 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 so sclk si v dd x out x in gnd v pp (f) (f) (f) (f) (f) (f) (f) (f) (f) (f) (f) (f)
4 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds pd6p8b pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) (1) normal operation mode (2) prom programming mode caution the item in parentheses indicates the processing of pins not used in the prom programming mode. f: these pins are pulled down internally, so leave them open. 1 2 3 4 5 6 7 8 9 10 k i/o6 k i/o7 s 0 s 1 /led rem v dd ic s 3 gnd s 2 20 19 18 17 16 15 14 13 12 11 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 so sclk si v dd gnd v pp (f) (f) (f) (f) (f) (f) (f) (f) (f) (f) (f) (f) (f) (f)
5 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds block diagram item pd6p8 pD6P8A pd6p8b rom capacity 2026 10 bits one-time prom ram capacity 32 4 bits stack 1 level (shared with rf of ram) i/o pins key input (k i ): 4 pins key i/o (k i/o ): 8 pins key expansion input (s 0 , s 1 , s 2 ): 3 pins remote control transmission display output (led): 1 pin (shared with s 1 pin) number of keys 32 keys 56 keys (when expanded by key expansion input) clock frequency ceramic oscillation f x = 3.5 to 4.5 mhz instruction execution time 16 s (@ f x = 4 mhz) carrier frequency the high-level and low-level width can be set separately from 250 ns to 64 s (@ f x = 4 mhz operation) via modulo registers timer 9-bit programmable timer: 1 channel, timer clock: f x /64 poc circuit on chip ram retention detector on chip internal oscillator not available on chip programming method parallel serial supply voltage v dd = 1.9 to 3.6 v operating ambient t a = ?0 to +85 c temperature package 20-pin plastic ssop (7.62 mm (300)) k i0 to k i3 k i/o0 to k i/o7 s 0 , s 1 /led, s 2 port k i port k i/o port s 4 8 3 4 8 3 ram system control carrier generator 9-bit timer cpu core x in x out v dd gnd rem s 1 /led one- time prom list of functions
6 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds contents 1. pin functions ................................................................................................................ ......... 8 1.1 normal operation mode ....................................................................................................... ............. 8 1.2 prom programming mode ....................................................................................................... ........ 10 1.3 pins i/o circuits ........................................................................................................... ...................... 11 1.4 recommended connection of unused pins ................................................................................... 12 1.5 notes on using k i pin after reset ................................................................................................... 12 2. differences between pd67a, 67b, 68a, 68b, and pd6p8, 6p8a, 6p8b .................. 13 3. internal cpu functions .................................................................................................. 14 3.1 program counter (pc): 11 bits ............................................................................................... ......... 14 3.2 stack pointer (sp): 1 bit ................................................................................................... ................ 14 3.3 address stack register (asr (rf)): 11 bits .................................................................................. .14 3.4 program memory (one-time prom): 2,026 steps 10 bits ......................................................... 15 3.5 data memory (ram): 32 4 bits ...................................................................................................... 16 3.6 data pointer (dp): 12 bits .................................................................................................. ............... 17 3.7 accumulator (a): 4 bits ..................................................................................................... ............... 17 3.8 arithmetic and logic unit (alu): 4 bits ..................................................................................... ..... 17 3.9 flags ....................................................................................................................... ............................ 18 3.9.1 status flag (f) ........................................................................................................... ............... 18 3.9.2 carry flag (cy) ........................................................................................................... ............. 18 4. port registers (px) ........................................................................................................ ... 19 4.1 k i/o port (p0) ..................................................................................................................... .................. 20 4.2 k i port/special ports (p1) ....................................................................................................... .......... 20 4.2.1 k i port (p 11 : bits 4 to 7 of p1) .................................................................................................. 20 4.2.2 s 0 port (bit 2 of p1) ............................................................................................................ ...... 21 4.2.3 s 1 /led port (bit 3 of p1) ........................................................................................................ .. 21 4.2.4 s 2 port (bit 1 of p1) ............................................................................................................ ...... 21 4.3 control register 0 (p3) ..................................................................................................... ................ 22 4.3.1 ram retention flag (bit 3 of p3) .......................................................................................... ..... 23 4.4 control register 1 (p4) ..................................................................................................... ................ 25 5. timer ........................................................................................................................ ................. 26 5.1 timer configuration ......................................................................................................... ................. 26 5.2 timer operation ............................................................................................................. .................... 27 5.3 carrier output .............................................................................................................. ...................... 29 5.3.1 carrier output generator .................................................................................................. ........ 29 5.3.2 carrier output control .................................................................................................... .......... 30 5.4 software control of timer output ............................................................................................ ....... 32 6. standby function ............................................................................................................ ... 33 6.1 outline of standby function ................................................................................................. ........... 33 6.2 standby mode setting and release ............................................................................................ ..... 34 6.3 standby mode release timing ................................................................................................. ....... 36 7. reset ........................................................................................................................ ................. 37
7 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 8. poc circuit ................................................................................................................. ........... 38 8.1 functions of poc circuit .................................................................................................... .............. 39 8.2 oscillation check at low supply voltage ..................................................................................... .. 39 9. system clock oscillator ( pd6p8, 6p8a) .................................................................. 40 10. instruction set ............................................................................................................ ....... 41 10.1 machine language output by assembler ....................................................................................... 41 10.2 circuit symbol description ................................................................................................. ............. 42 10.3 mnemonic to/from machine language (assembler output) contrast table ............................... 43 10.4 accumulator manipulation instructions ...................................................................................... .... 47 10.5 i/o instructions ........................................................................................................... ....................... 50 10.6 data transfer instructions ................................................................................................. ............... 51 10.7 branch instructions ........................................................................................................ .................. 53 10.8 subroutine instructions .................................................................................................... ................ 54 10.9 timer operation instructions ............................................................................................... ............ 55 10.10 others .................................................................................................................... ............................. 58 11. assembler reserved words ........................................................................................ 60 11.1 mask option directives ..................................................................................................... ................ 60 11.1.1 option and endop quasi-directives .................................................................................... 60 11.1.2 mask option definition quasi-directives .................................................................................. .60 12. writing and verifying one-time prom (program memory) ( pd6p8) ................. 61 12.1 operating mode when writing/verifying program memory .......................................................... 61 12.2 program memory writing procedure ........................................................................................... .... 62 12.3 program memory reading procedure ........................................................................................... .. 63 13. writing and verification of one-time prom (program memory) ( pD6P8A, 6p8b) ......... 64 13.1 initialization ............................................................................................................. ........................... 64 13.2 serial communication format ................................................................................................ ......... 65 13.3 writing of program memory .................................................................................................. ........... 66 13.4 reading of program memory .................................................................................................. ......... 66 14. electrical specifications ( pd6p8) ............................................................................. 67 15. electrical specifications ( pD6P8A) .......................................................................... 74 16. electrical specifications ( pd6p8b) (target) ........................................................ 79 17. characteristic curves (reference values) ( pd6p8) ....................................... 84 18. application circuit example .......................................................................................... 85 19. package drawing ............................................................................................................. ... 88 20. recommended soldering conditions .......................................................................... 89 appendix a. development tools ......................................................................................... 90 appendix b. example of remote control transmission format (in the case of nec transmission format in command one-shot transmission mode) ........ 91
8 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 1. pin functions 1.1 normal operation mode (1) pd6p8, 6p8a pin no. symbol function output format after reset 1 k i/o0 to k i/o7 cmos high-level output 2 push-pull note 1 15 to 20 3s 0 high-impedance (off mode) 4s 1 /led cmos push-pull high-level output (led) 5 rem cmos push-pull low-level output 6v dd 7x out low level 8x in (oscillation stopped) 9 gnd 10 s 2 input (high impedance, stop mode release cannot be used) 11 to 14 k i0 to input (low-level) k i3 note 2 notes 1. note that the drive capability of the low-level output side is held low. 2. in order to prevent malfunction, do not input a high-level signal to pins k i0 to k i3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when poc is released due to supply voltage startup. 8-bit i/o port. i/o mode can be switched in 8-bit units. in input mode, a pull-down resistor is added. in output mode, these pins can be used as a key scan outputs from the key matrix. input port. this pin can also be used as a key return input from the key matrix. in input mode, the use of a pull-down resistor for the s 0 and s 1 ports can be specified by software in 2-bit units. if input mode is released by software, this pin is placed in the off mode and enters a high-impedance state. i/o port. in input mode (s 1 ), this pin can also be used as a key return input from the key matrix. the use of a pull-down resistor for the s 0 and s 1 ports can be specified by software in 2-bit units. in output mode (led), this pin becomes the remote control transmission display output (active low). when the remote control carrier is output from the rem output, this pin outputs a low level from the led output in synchronization with the rem signal. infrared remote control transmission output. the output is active high. the carrier high-level and low-level width can each be freely set in a range of 250 ns to 64 s (@ f x = 4 mhz) using software. power supply these pins are connected to system clock ceramic resonators. gnd pin input port. the use of the stop mode release of the s 2 port can be specified by software. when using this pin as a key input from the key matrix, enable the use of the stop mode release (at this time, a pull-down resistor is connected internally.) when the stop mode release is disabled, this pin can be used as an input port that does not release the stop mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) 4-bit input port. these pins can be used as key return inputs to the key matrix. the use of pull-down resistors can be specified by software in 4-bit units.
9 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds (2) pd6p8b pin no. symbol function output format after reset 1 k i/o0 to k i/o7 cmos high-level output 2 push-pull note 1 15 to 20 3s 0 high-impedance (off mode) 4s 1 /led cmos push-pull high-level output (led) 5 rem cmos push-pull low-level output 6v dd 7ic 9 gnd 8s 3 input 10 s 2 (high impedance, stop mode release cannot be used) 11 to 14 k i0 to input (low-level) k i3 note 2 notes 1. note that the drive capability of the low-level output side is held low. 2. in order to prevent malfunction, do not input a high-level signal to pins k i0 to k i3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when poc is released due to supply voltage startup. 8-bit i/o port. i/o mode can be switched in 8-bit units. in input mode, a pull-down resistor is added. in output mode, these pins can be used as a key scan outputs from the key matrix. input port. this pin can also be used as a key return input from the key matrix. in input mode, the use of a pull-down resistor for the s 0 and s 1 ports can be specified by software in 2-bit units. if input mode is released by software, this pin is placed in the off mode and enters a high-impedance state. i/o port. in input mode (s 1 ), this pin can also be used as a key return input from the key matrix. the use of a pull-down resistor for the s 0 and s 1 ports can be specified by software in 2-bit units. in output mode (led), this pin becomes the remote control transmission display output (active low). when the remote control carrier is output from the rem output, this pin outputs a low level from the led output in synchronization with the rem signal. infrared remote control transmission output. the output is active high. the carrier high-level and low-level width can each be freely set in a range of 250 ns to 64 s (@ f x = 4 mhz) using software. power supply internally connected pin gnd pin input port. the use of the stop mode release of the s 2 and s 3 ports can be specified by software. when using these pins as a key input from the key matrix, enable the use of the stop mode release (at this time, a pull-down resistor is connected internally.) when the stop mode release is disabled, these pins can be used as an input port that does not release the stop mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) 4-bit input port. these pins can be used as key return inputs to the key matrix. the use of pull-down resistors can be specified by software in 4-bit units.
10 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 1.2 prom programming mode (1) pd6p8 pin no. symbol function i/o 1, 2 d 0 to d 7 8-bit data i/o when writing/verifying program memory i/o 15 to 20 3c lk clock input for updating address when writing/verifying program input memory 6v dd power supply supply +3 v to this pin when writing/verifying program memory. 7x out clock necessary for writing program memory. connect a 4 mhz ceramic 8x in resonator to these pins. input 9 gnd gnd 10 v pp supplies voltage for writing/verifying program memory. apply +10.5 v to this pin. 11 to 14 md 0 to md 3 input for selecting operation mode when writing/verifying program memory input (2) pD6P8A pin no. symbol function i/o 2s o serial data output when verifying program memory output 3 sclk clock input when writing/verifying program memory input 4s i serial data input when writing program memory input 6v dd power supply supply +3 v to this pin when writing/verifying program memory. 7x out clock necessary for writing program memory. connect a 4 mhz ceramic 8x in resonator to these pins. input 9 gnd gnd 10 v pp supplies voltage for writing/verifying program memory. apply +10.5 v to this pin. (3) pd6p8b pin no. symbol function i/o 2s o serial data output when verifying program memory output 3 sclk clock input when writing/verifying program memory input 4s i serial data input when writing program memory input 6v dd power supply supply +3 v to this pin when writing/verifying program memory. 9 gnd gnd 10 v pp supplies voltage for writing/verifying program memory. apply +10.5 v to this pin.
11 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 1.3 pins i/o circuits the i/o circuits of the pd6p8, 6p8a, 6p8b pins are shown in partially simplified forms below. (1) k i/o0 to k i/o7 (4) s 0 (5) s 1 /led (2) k i0 to k i3 (3) rem (6) s 2 , s 3 note 2 p-ch n-ch note 1 n-ch v dd output latch input buffer data output disable selector n-ch input buffer pull-down flag standby release p-ch n-ch v dd output latch carrier generator data off mode pull-down flag n-ch input buffer standby release p-ch n-ch n-ch v dd rem output latch input buffer output disable pull-down flag standby release n-ch input buffer stop release on/off standby release notes 1. the drive capability is held low. 2. pd6p8b only
12 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 1.4 recommended connection of unused pins the following connections are recommended for unused pins in the normal operation mode. table 1-1. connections for unused pins pin connection inside the microcontroller outside the microcontroller k i/o0 -k i/o7 input mode leave open output mode high-level output rem ic note s 1 /led output mode (led) setting s 0 off mode setting directly connect these pins s 2 , s 3 note to gnd k i0 -k i3 note pd6p8b only caution the i/o mode and the pin output level are recommended to be fixed by setting them repeatedly in each loop of the program. 1.5 notes on using k i pin after reset in order to prevent malfunction, do not input a high-level signal to pins k i0 to k i3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when poc is released due to supply voltage startup.
13 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 2. differences between pd67a, 67b, 68a, 68b, and pd6p8, 6p8a, 6p8b table 2-1 shows the differences between the pd67a, 67b, 68a, 68b, and pd6p8, 6p8a, 6p8b. the only differences between these models are the program memory, ram retention detection voltage, internal oscillator, poc detection voltage, and supply voltage; the other cpu functions and internal peripheral hardware are the same. the electrical specifications also differ slightly. for the electrical specifications, refer to the data sheet of each model. table 2-1. differences between pd67a, 67b, 68a, 68b, and pd6p8, 6p8a, 6p8b item pd6p8 pD6P8A pd6p8b pd67a pd67b pd68a pd68b rom one-time prom mask rom 2026 10 bits 1002 10 bits 2026 10 bits poc detection voltage v poc = 1.8 v v poc = 1.85 v v poc = 1.5 v v poc = 1.85 v v poc = 1.5 v (typ.) (typ.) (typ.) (typ.) (typ.) ram retention v id = 1.8 v v id = 1.6 v v id = 1.4 v v id = 1.5 v v id = 1.4 v v id = 1.5 v detection voltage (typ.) (typ.) (typ.) (typ.) (typ.) (typ.) internal oscillator f x = 4 mhz (typ.) supply voltage v dd = 1.9 to 3.6 v v dd = 2.0 to 3.6 v v dd = 1.65 to 3.6 v v dd = 2.0 to 3.6 v v dd = 1.65 to 3.6 v electrical specifications some electrical specifications, such as data retention voltage and current consumption, differ. refer to data sheet of each model for details.
14 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 3. internal cpu functions 3.1 program counter (pc): 11 bits the program counter (pc) is a binary counter that holds the address information of the program memory. figure 3-1. program counter configuration the pc contains the address of the instruction that should be executed next. normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. however, when executing jump instructions (jmp, jc, jnc, jf, jnf), the pc contains the jump destination address written in the operand. when executing the subroutine call instruction (call), the call destination address written in the operand is entered in the pc after the pc contents at the time are saved in the address stack register (asr). if the return instruction (ret) is executed after the call instruction is executed, the address saved in the asr is restored to the pc. after reset, the value of the pc becomes ?00h? 3.2 stack pointer (sp): 1 bit this is a 1-bit register that holds the status of the address stack register. the stack pointer contents are incremented when the call instruction (call) is executed and decremented when the return instruction (ret) is executed. when reset, the stack pointer contents are cleared to 0. when the stack pointer overflows (stack level 2 or more) or underflows, the cpu is defined as hung up, a system reset signal is generated, and the pc becomes 000h. as no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program. 3.3 address stack register (asr (rf)): 11 bits the address stack register saves the return address of the program after a subroutine call instruction is executed. the lower 8 bits are allocated in rf of the data memory as a alternate-function ram. the register holds the asr value even after the ret instruction is executed. after reset, it holds the previous data (undefined when turning on the power). caution if rf is accessed as the data memory, the higher 4 bits become undefined. figure 3-2. address stack register configuration pc9 pc10 pc0 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc asr10 asr9 asr8 asr7 asr6 asr5 asr4 asr3 asr2 asr1 asr0 asr rf
15 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 3.4 program memory (one-time prom): 2,026 steps 10 bits the one-time prom consists of 10 bits per step, and is addressed by the program counter. the program memory stores programs and table data, etc. the 22 steps from feah to fffh cannot be used in the test program area. figure 3-3. program memory map note the test program area is designed so that a program or data placed in either of them by mistake is returned to the 000h address. 0 3 4 7 7 7 test program area note page 0 page 1 10 bits h h h h h h 0 f 0 9 a f 0 f 0 e e f
16 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 3.5 data memory (ram): 32 4 bits the data memory, which is a static ram consisting of 32 4 bits, is used to retain processed data. the data memory is sometimes processed in 8-bit units. r0 can be used as the rom data pointer. rf is also used as the asr. after reset, r0 is cleared to 00h and r1 to rf retain the previous data (undefined when turning on the power). figure 3-4. data memory configuration notes 1. r0 alternately functions as the rom data pointer (refer to 3.6 data pointer (dp) ). 2. rf alternately functions as the pc address stack (refer to 3.3 address stack register (asr (rf) ). r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 ra rb rc rd re rf r 10 r 00 r 11 r 01 r 12 r 02 r 13 r 03 r 14 r 04 r 15 r 05 r 16 r 06 r 17 r 07 r 18 r 08 r 19 r 09 r 1a r 0a r 1b r 0b r 1c r 0c r 1d r 0d r 1e r 0e r 1f r 0f note 1 note 2 r 1n (higher 4 bits) r 0n (lower 4 bits)
17 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 3.6 data pointer (dp): 12 bits the rom data table can be referenced by setting the rom address in the data pointer to call the rom contents. the lower 8 bits of the rom address are specified by r0 of the data memory; and the higher 4 bits by bits 4 to 7 of the p3 register (cr0). after reset, the pointer contents become 000h. figure 3-5. data pointer configuration 3.7 accumulator (a): 4 bits the accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various operations. after reset, the accumulator contents are left undefined. figure 3-6. accumulator configuration a 3 a 2 a 1 a 0 a 3.8 arithmetic and logic unit (alu): 4 bits the arithmetic and logic unit (alu), which refers to an arithmetic circuit consisting of 4 bits, executes simple (mainly logical) operations. r 00 dp 9 dp 8 dp 7 dp 6 dp 5 dp 4 dp 3 dp 2 dp 1 dp 0 r 10 r0 b 4 b 5 p3 register p 3 dp 10 b 6 0 b 7
18 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 3.9 flags 3.9.1 status flag (f) pin and timer statuses can be checked by executing the stts instruction to check the status flag. the status flag is set (to 1) in the following cases. if the condition specified with the operand is met when the stts instruction is executed when standby mode is released. when the release condition is met at the point of executing the halt instruction. (in this case, the system does not enter the standby mode.) conversely, the status flag is cleared (to 0) in the following cases: if the condition specified with the operand is not met when the stts instruction is executed. when the status flag has been set (to 1), the halt instruction executed, but the release condition is not met at the point of executing the halt instruction. (in this case, the system does not enter the standby mode.) table 3-1. conditions for status flag (f) to be set by stts instruction operand value of stts instruction condition for status flag (f) to be set b 3 b 2 b 1 b 0 0000 high level is input to at least one of k i pins. 011 high level is input to at least one of k i pins. 110 high level is input to at least one of k i pins. 101 the down counter of the timer is 0. 1 either of the combinations [the following condition is added in addition to the above.] of b 2 , b 1 , and b 0 above. high level is input to at least one of s 0 note 1 , s 1 note 1 , or s 2 note 2 pins. notes 1. the s 0 and s 1 pins must be set to input mode (bit 2 and bit 0 of the p4 register are set to 0 and 1, respectively). 2. the use of stop mode release for the s 2 pin must be enabled (bit 3 of the p4 register is set to 1). 3.9.2 carry flag (cy) the carry flag is set (to 1) in the following cases: if the anl instruction or the xrl instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the operand is 1. if the rl instruction or the rlz instruction is executed when bit 3 of the accumulator is 1. if the inc instruction or the scaf instruction is executed when the value of the accumulator is 0fh. the carry flag is cleared (to 0) in the following cases: if the anl instruction or the xrl instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is 0. if the rl instruction or the rlz instruction is executed when bit 3 of the accumulator is 0. if the inc instruction or the scaf instruction is executed when the value of the accumulator is other than 0fh. if the orl instruction is executed. when data is written to the accumulator by the mov instruction or the in instruction.
19 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 4. port registers (px) the k i/o port, the k i port, the special ports (s 0 , s 1 /led, s 2 ), and the control registers are treated as port registers. after reset, the port register values are as shown below. figure 4-1. port register configuration notes 1. : refers to the value based on the k i and s 2 pin state. 2. : refers to the value based on decrease of power supply voltage (0 when v dd v id ) remark v id : ram retention detection voltage table 4-1. relationship between ports and reading/writing port name input mode output mode read write read write k i/o pin state output latch output latch output latch k i pin state s 0 pin state note s 1 /led pin state pin state s 2 pin state note when in off mode, ??is always read. port register p0 k i/o7 p 00 after reset ffh k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 p 10 p1 k i3 p 01 11 1b note 1 k i2 k i1 k i0 s 1 /led s 0 s 2 1 p 11 p3 (control register 0) dp 11 p 03 0000 000b note 2 dp 10 dp 9 dp 8 ram retention flag p 13 p4 (control register 1) 0 p 04 26h 0 k i pull-down s 0 /s 1 pull-down s 2 stop release s 1 /led mode k i/o mode s 0 mode p 14
20 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 4.1 k i/o port (p0) the k i/o port is an 8-bit i/o port for key scan output. i/o mode is set by bit 1 of the p4 register. if a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. if a write instruction is executed, data can be written to the output latch regardless of input or output mode. after reset, the port is placed in output mode and the value of the output latch (p0) becomes 1111 1111b. the k i/o port incorporates a pull-down resistor, allowing pull-down in input mode only. caution when a key is double-pressed, a high-level output and a low-level output may conflict at the k i/o port. to avoid this, the low-level output current of the k i/o port is held low. therefore, be careful when using the k i/o port for purposes other than key scan output. the k i/o port is designed so that even when connected directly to v dd within the normal supply voltage range (v dd = 1.9 to 3.6 v), no problem occurs. table 4-2. k i/o port (p0) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 b 0 to b 7 :w hen reading: in input mode, the k i/o pin? state is read. in output mode, the k i/o pin? output latch contents are read. when writing: data is written to the k i/o pin? output latch regardless of input or output mode. 4.2 k i port/special ports (p1) 4.2.1 k i port (p 11 : bits 4 to 7 of p1) the k i port is a 4-bit input port for key input. the pin state can be read. the use of a pull-down resistor for the k i port can be specified in 4-bit units by software using bit 5 of the p4 register. after reset, a pull-down resistor is connected. table 4-3. k i /special port register (p1) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name k i3 k i2 k i1 k i0 s 1 /led s 0 s 2 fixed to ? b 1 : the state of the s 2 pin is read (read only). b 2 : in input mode, state of the s 0 pin is read (read only). in off mode, this bit is fixed to 1. b 3 : the state of the s 1 /led pin is read regardless of input/output mode (read only). b 4 to b 7 : the state of the k i pin is read (read only). caution in order to prevent malfunction, be sure to input a low level to one or more of pins k i0 to k i3 when poc is released by supply voltage rising (can be left open. when open, leave the pull- down resistor connected).
21 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 4.2.2 s 0 port (bit 2 of p1) the s 0 port is an input/off mode port. the pin state can be read by setting this port to input mode using bit 0 of the p4 register. in input mode, the use of a pull-down resistor for the s 0 and s 1 /led port can be specified in 2-bit units by software using bit 4 of the p4 register. if input mode is released (thus set to off mode), the pin becomes high-impedance but is configured so that through current does not flow internally. in off mode, 1 can be read regardless of the pin state. after reset, s 0 is set to off mode, thus becoming high-impedance. 4.2.3 s 1 /led port (bit 3 of p1) the s 1 /led port is an i/o port. input or output mode can be set using bit 2 of the p4 resister. the pin state can be read in both input mode and output mode. when in input mode, the use of a pull-down resistor for the s 0 and s 1 /led ports can be specified in 2- bit units by software using bit 4 of the p4 register. when in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote control transmission display pin (refer to 5 timer ). after reset, s 1 /led is placed in output mode, and a high level is output. 4.2.4 s 2 port (bit 1 of p1) the s 2 port is an input port. use of stop mode release for the s 2 port can be specified by bit 3 of the p4 register. when using the pin as a key input from a key matrix, enable (bit 3 of the p4 register is set to 1) the use of stop mode release (at this time, a pull-down resistor is connected internally.) when stop mode release is disabled (bit 3 of the p4 register is set to 0), it can be used as an input port that does not release the stop mode even if the release condition is met (at this time, a pull-down resistor is not connected internally.) the state of the pin can be read in both cases. after reset, s 2 is set to input mode where the stop mode release is disabled, and enters a high-impedance state.
22 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 4.3 control register 0 (p3) control register 0 consists of 8 bits. the contents that can be controlled are as shown below. after reset, the register becomes 0000 000b note . note : refers to the value based on a decrease of power supply voltage (0 when v dd v id ) remark v id : ram retention detection voltage table 4-4. control register 0 (p3) bit b 7 note b 6 b 5 b 4 b 3 b 2 b 1 b 0 nam e dp (data pointer) dp 11 dp 10 dp 9 dp 8 setting 0 0 0 0 0 not retainable fixed to 0 11 111 retainable after reset 0 0 0 0 0 0 0 0 b 3 : ram retention flag. for function details, refer to 4.3.1 ram retention flag (bit 3 of p3) . b 4 to b 7 : specify the higher bits of the rom data pointer (dp 8 to dp 11 ). note set b 7 to 0 in the case of the pd6p8, 6p8a, 6p8b. ram retention flag
23 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 4.3.1 ram retention flag (bit 3 of p3) the ram retention flag indicates whether the supply voltage has fallen below the level at which the contents of the ram are lost while the battery is being exchanged or when the battery voltage has dropped. this flag is at bit 3 of control register 0 (p3). it is cleared to 0 if the supply voltage drops below the ram retention detection voltage. if this flag is 0, it can be judged that the ram contents have been lost or that power has just been applied. this flag can be used to initialize the ram via software. after initializing the ram and writing the necessary data to it, set this ram retention flag to 1 by software. at this time, 1 means that data has been set to the ram. figure 4-2. supply voltage transition and detection voltage ( pd6p8) v dd v poc /v id 0 v ram retention flag (a) (4) (3) (2) set to 1 flag contents are read (1) t poc detection voltage/ ram retention detection voltage v poc = v id = 1.8 v (typ.) (1) if the supply voltage rises after the battery has been set, and exceeds v poc (poc detection voltage), reset is cleared. because the supply voltage rises from 0 v, which is lower than v id (ram retention detection voltage), the ram retention flag remains in the initial status 0. (2) the supply voltage has now risen to the level at which the device can operate. write the necessary data to the ram and set the ram retention flag to 1. (3) the device is reset if the supply voltage drops below v poc . at point (a) in the figure, the voltage is lower than v id . consequently, the ram retention flag is cleared to 0. (4) if the ram retention flag is checked by software after reset has been cleared, it is 0. this means that the contents of the ram may have been lost. if this case, initialize the ram by software. cautions 1. the software developed for the pd67a, 68a and 69a (using the ram retention flag) can be used for the pd6p8 as is. 2. unlike the pd67a, 68a and 69a, the ram retention detection voltage of the pd6p8 is the same as the poc detection voltage. when software is newly developed, it is not necessary to use the ram retention flag if only the ram is initialized by reset.
24 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds figure 4-3. supply voltage transition and detection voltage ( pD6P8A, 6p8b) (1) if the supply voltage rises after the battery has been set, and exceeds v poc (poc detection voltage), reset is cleared. because the supply voltage rises from 0 v, which is lower than v id (ram retention detection voltage), the ram retention flag remains in the initial status 0. (2) the supply voltage has now risen to the level at which the device can operate. write the necessary data to the ram and set the ram retention flag to 1. (3) the device is reset if the supply voltage drops below v poc . at point (a) in the above figure, the ram retention flag remains 1 because the supply voltage is higher than v id at this point. (4) if the ram retention flag is checked by software after reset has been cleared, it is 1. this means that the contents of the ram have not been lost. it is therefore not necessary to initialize the ram by software. (5) the device is reset if the supply voltage drops below v poc . at point (b) in the figure, the voltage is lower than v id . consequently, the ram retention flag is cleared to 0. (6) if the ram retention flag is checked by software after reset has been cleared, it is 0. this means that the contents of the ram may have been lost. if this case, initialize the ram by software. v dd v poc v id 0 v ram retention flag (a) (b) (6) (5) (4) (3) (2) set to 1 flag contents are read flag contents are read (1) t poc detection voltage (refer to 8. poc circuit ) v poc = 1.8 v (typ.) ram retention detection voltage v id = 1.6 v (typ.)
25 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 4.4 control register 1 (p4) control register 1 consists of 8 bits. the contents that can be controlled are as shown below. after reset, the register becomes 0010 0110b. table 4-5. control register 1 (p4) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name k i s 0 /s 1 s 2 s 1 /led k i/o s 0 pull-down pull-down stop release mode mode mode setting 0 fixed fixed off off disable s 1 in off 1 to 0 to 0 on on enable led out in after reset 00100110 b 0 : specifies the input mode of the s 0 port. 0 = off mode (high impedance); 1 = in (input mode). b 1 : specifies the i/o mode of the k i/o port. 0 = in (input mode); 1 = out (output mode). b 2 : specifies the i/o mode of the s 1 /led port. 0 = s 1 (input mode); 1 = led (output mode). b 3 : specified the use of stop mode release by s 2 port (with/without pull-down resistor). 0 = disable (without pull-down); 1 = enable (with pull-down). b 4 : specifies the use of a pull-down resistor in s 0 /s 1 port input mode. 0 = off (not used); 1 = on (used) b 5 : specifies the use of a pull-down resistor for the k i port. 0 = off (not used); 1 = on (used). remark in output mode or in off mode, all the pull-down resistors are automatically disconnected.
26 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 5. timer 5.1 timer configuration the timer is the block used for creating a remote control transmission pattern. as shown in figure 4-1, it consists of a 9-bit down counter (t 8 to t 0 ), a flag (t 9 ) permitting the 1-bit timer output, and a zero detector. figure 5-1. timer configuration s 1 /led rem carrier synchronous circuit carrier signal zero detector 9-bit down counter t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 t t1 f x /64 timer operation end signal (halt # 101b release signal) count clock t0
27 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 5.2 timer operation the timer starts (counting down) when a value other than 0 is set for the down counter with a timer manipulation instruction. the timer manipulation instructions for making the timer start operation are shown below: mov t0, a mov t1, a mov t, #data10 mov t, @r0 the down counter is decremented (?) in the cycle of 64/f x . if the value of the down counter becomes 0, the zero detector generates the timer operation end signal to stop the timer operation. at this time, if the timer is in halt mode (halt # 101b) waiting for the timer to stop its operation, the halt mode is released and the instruction following the halt instruction is executed. the output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. the following relational expression applies between the timer? output time and the down counter? set value. timer output time = (set value + 1) 64/f x ?4/f x in addition, when the timer is set successively, the timer output time is also 4/f x shorter than the total time. an example is shown below. example when f x = 4 mhz mov t, #3ffh stts #05h halt #05h mov t, #232h stts #05h halt #05h in the case above, the timer output time is as follows. (set value + 1) 64/f x + (set value + 1) 64/f x ?4/f x = (511 + 1) 64/4 + (50 + 1) 64/4 ?4/4 = 9.007 ms
28 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds by setting the flag (t 9 ) that enables the timer output to 1, the timer can output its operation status from the s 1 / led pin and the rem pin. the rem pin can also output the carrier while the timer is in operation. table 5-1. timer output (at t 9 = 1) s 1 /led pin rem pin timer operating low level high level (or carrier output note ) timer halting high level low level note the carrier output results if bit 9 (cary) of the high-level period setting modulo register (mod1) is cleared (to 0). figure 5-2. timer output (when carrier is not output) timer output time: (set value + 1) 64/f x ?4/f x led rem 4/f x
29 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 5.3 carrier output 5.3.1 carrier output generator the carrier generator consists of a 9-bit counter and two modulo registers for setting the high- and low-level periods (mod1 and mod0 respectively). figure 5-3. configuration of remote controller carrier generator notes 1. bit 9 of the modulo register for setting the low-level period (mod0) is fixed to 0. 2. t 9 : flag that enables timer output (timer block) (see figure 5-1 timer configuration ) the carrier duty ratio and carrier frequency can be determined by setting the high- and low-level widths using the respective modulo registers. each of these widths can be set in a range of 250 ns to 64 s (@ f x = 4 mhz). the system clock multiplied by 2 is used for the 9-bit counter input (8 mhz when f x = 4 mhz). mod0 and mod1 are read and written using timer manipulation instructions. mov a, m00 mov m00, a mov m0, #data10 mov a, m01 mov m01, a mov m1, #data10 mov a, m10 mov m10, a mov m0, @r0 mov a, m11 mov m11, a mov m1, @r0 the values of mod0 and mod1 can be calculated from the following expressions. mod0 = (2 f x (1 ?d) t) ?1 mod1 = (2 f x d t) ?1 caution be sure to input values in range of 001h to 1ffh to mod0 and mod1. remark d: carrier duty ratio (0 < d < 1) f x : input clock (mhz) t: carrier cycle ( s) carrier signal f/f match clear m11 t 9 cary modulo register for setting the high-level period (mod1) modulo register for setting the low-level period (mod0) note 1 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 t 8 0t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 2f x f x f x t 9 note 2 m10 m1 m01 selector comparator 9-bit counter multiplier m00 m0
30 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 5.3.2 carrier output control remote controller carrier can be output from the rem pin by clearing (0) bit 9 (cary) of the modulo register for setting the high-level period (mod1). when performing carrier output, be sure to set the timer operation after setting the mod0 and mod1 values. note that a malfunction may occur if the values of mod0 and mod1 are changed while carrier is being output from the rem pin. executing the timer manipulation instruction starts the carrier output from the low level. if the timer? down counter reaches 0 during carrier output, carrier output is stopped and the rem pin becomes low level. if the down counter reaches 0 while the carrier output is high level, carrier output will stop after first becoming low level following the set period of high level. figure 5-4. timer output (when carrier is output) note if the down counter reaches 0 while the carrier output is high level, carrier output will stop after becoming low level. timer output time: (set value + 1) 64/f x ?4/f x led rem note t h t l timer manipulation instruction 4/f x
31 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds output from the rem pin is as follows, in accordance with the values set to bit 9 (cary) of mod1 and the timer output enable flag (t 9 ), and the value of the timer block? 9-bit down counter (t 0 to t 8 ). table 5-2. rem pin output mod1 bit 9 (cary) timer output enable flag 9-bit down counter rem pin (timer block t 9 ) (timer block t 0 to t 8 ) 0 low-level output ? other than 0 01 carrier output note 1 high-level output note input values in the range of 001h to 1ffh to mod0 and mod1. caution mod0 and mod1 must be set while the rem pin is low level (t 9 = 0 or t 0 to t 8 = 0). table 5-3. example of carrier frequency settings (f x = 4 mhz) setting value t h ( s) 0.25 1.0 2.5 5.0 8.25 8.25 8.75 8.75 8.75 9.0 9.125 13.25 15.0 25.0 32.0 mod1 01h 07h 13h 27h 41h 41h 45h 45h 45h 47h 48h 69h 77h c7h ffh mod0 01h 0bh 13h 27h 41h 85h 89h 8bh 8ch 91h 94h d5h 77h c7h ffh t l ( s) 0.25 1.5 2.5 5.0 8.25 16.75 17.25 17.5 17.625 18.25 18.625 26.75 15.0 25.0 32.0 t ( s) 0.5 2.5 5.0 10 16.5 25 26.0 26.25 26.375 27.25 27.75 40.0 30.0 50.0 64.0 f c (khz) 2,000 400 200 100 60.6 40 38.5 38.10 37.9 36.7 36.0 25 33.3 20 15.6 duty 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/2 1/2 1/2 t h t l t carrier signal
32 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 5.4 software control of timer output the timer output can be controlled by software. as shown in figure 4-5, a pulse with a minimum width of 64/f x - 4/f x can be output. figure 5-5. output of pulse of 1-instruction cycle width . . . mov t, #0000000000b; low-level output from the rem pin . . . mov t, #1000000000b; high-level output from the rem pin mov t, #0000000000b; low-level output from the rem pin . . . 64/f x ?4/f x led rem 4/f x
33 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 6. standby function 6.1 outline of standby function to save current consumption, two types of standby modes, i.e., halt mode and stop mode, have been provided available. in stop mode, the system clock stops oscillation. at this time, the x in and x out pins are fixed to a low level. in halt mode, cpu operation halts, while the system clock continues oscillation. when in halt mode, the timer (including rem output and led output) operates. in either stop mode or halt mode, the statuses of the data memory, accumulator, and port registers, etc. immediately before the standby mode is set are retained. therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. table 6-1. statuses during standby mode stop mode halt mode setting instruction halt instruction clock oscillator oscillation stopped oscillation continued cpu operation halted data memory immediately preceding status retained operation accumulator immediately preceding status retained statuses flag f 0 (when 1, the flag is not placed in the standby mode.) cy immediately preceding status retained port register immediately preceding status retained timer operation halted operable (the count value is reset to ?? cautions 1. write the nop instruction as the first instruction after stop mode is released. 2. when standby mode is released, the status flag (f) is set (to 1). 3. if, at the point the standby mode has been set, its release condition is met, then the system does not enter the standby mode. however, the status flag (f) is set (1).
34 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 6.2 standby mode setting and release the standby mode is set with the halt #b 3 b 2 b 1 b 0 b instruction for both stop mode and halt mode. for the standby mode to be set, the status flag (f) is required to have been cleared (to 0). the standby mode is released by the release condition specified with the reset (poc) or the operand of halt instruction. if the standby mode is released, the status flag (f) is set (to 1). even when the halt instruction is executed in the state that the status flag (f) has been set (to 1), the standby mode is not set. if the release condition is not met at this time, the status flag is cleared (to 0). if the release conditio n is met, the status flag remains set (to 1). even in the case when the release condition has been already met at the point that the halt instruction is executed, the standby mode is not set. here, also, the status flag (f) is set (to 1). caution depending on the status of the status flag (f), the halt instruction may not be executed. be careful about this. for example, when setting halt mode after checking the key status with the stts instruction, the system does not enter halt mode as long as the status flag (f) remains set (to 1) and thus sometimes performs an unintended operation. in this case, the intended operation can be realized by executing the stts instruction immediately after setting the timer to clear (to 0) the status flag. example stts #03h ;to check the k i pin status. mov t, #0xxh ;to set the timer stts #05h ;to clear the status flag (during this time, be sure not to execute an instruction that may set the status flag.) halt #05h ;to set halt mode table 6-2. addresses executed after standby mode release release condition address executed after release reset address 0 release condition shown in table 5-3 the address following the halt instruction
35 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds table 6-3. standby mode setup (halt #b 3 b 2 b 1 b 0 b) and release conditions operand value of halt instruction setting mode precondition for setup release condition b 3 b 2 b 1 b 0 0000 stop all k i/o pins are high-level output. high level is input to at least one of k i pins. 011 stop all k i/o pins are high-level output. high level is input to at least one of k i pins. 110 stop note 1 the k i/o0 pin is high-level output. high level is input to at least one of k i pins. 1 any of the stop [the following condition is added in addition to the above.] combinations of high level is input to at least one b 2 b 1 b 0 above of s 0 , s 1 and s 2 pins note 2 . 0/1 101 halt when the timer? down counter is 0 notes 1. when setting halt # 110b, configure a key matrix by using the k i/o0 pin and the k i pin so that the standby mode can be released. 2. at least one of the s 0 , s 1 and s 2 pins (the pin used for releasing the standby mode) must be specified as follows: s 0 , s 1 pins: input mode (specified by bits 0 and 2 of the p4 register) s 2 pin: use of stop mode release enabled (specified by bit 3 of the p4 register) cautions 1. the internal reset takes effect when the halt instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the halt instruction. 2. if stop mode is set when the timer? down counter is not 0 (timer operating), the system is placed in stop mode only after all the 10 bits of the timer? down counter and the timer output permit flag are cleared to 0. 3. write the nop instruction as the first instruction after stop mode is released.
36 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 6.3 standby mode release timing (1) stop mode release timing figure 6-1. stop mode release by release condition caution when a release condition is met in the stop mode, the device is released from the stop mode, and goes into a wait state. at this time, if the release condition is not held, the device goes into stop mode again after the wait time has elapsed. therefore, when releasing the stop mode, it is necessary to hold the release condition longer than the wait time. (2) halt mode release timing figure 6-2. halt mode release by release condition wait (52/f x + ) halt mode operation mode stop mode oscillation stopped oscillation operation mode oscillation halt instruction (stop mode) standby release signal clock : oscillation growth time halt mode operation mode oscillation operation mode halt instruction (halt mode) standby release signal clock
37 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 7. reset a system reset is effected by the following causes: ?when the poc circuit has detected low power-supply voltage ?when the operand value is illegal or does not satisfy the precondition when the halt instruction is executed ?when the accumulator is 0h when the rlz instruction is executed ?when stack pointer overflows or underflows table 7-1. hardware statuses after reset hardware reset by on-chip poc circuit during operation reset by the on-chip poc circuit during reset by other factors note 1 standby mode pc (11 bits) 000h sp (1 bit) 0b data r0 = dp 000h memory r1 to rf undefined accumulator (a) undefined status flag (f) 0b carry flag (cy) 0b timer (10 bits) 000h port register p0 ffh p1 11 1b note 2 control register p3 0000 000b note 3 p4 26h notes 1. the following resets are available. reset when executing the halt instruction (when the operand value is illegal or does not satisfy the precondition) reset when executing the rlz instruction (when a = 0) reset by stack pointer? overflow or underflow 2. : refers to the value by the k i or s 2 pin status. in order to prevent malfunction, be sure to input a low level to one or more of pins k i0 to k i3 when poc is released by supply voltage rising (can be left open. when open, leave the pull-down resistor connected). 3. : refers to the value based on a decrease of power supply voltage (0 when v dd v id ). remark v id : ram retention detection voltage
38 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 8. poc circuit the poc circuit monitors the power supply voltage and applies an internal reset to the microcontroller when the battery is replaced. cautions 1. there are cases in which the poc circuit cannot detect a low power supply voltage of less than 1 ms. therefore, if the power supply voltage has become low for a period of less than 1 ms, the poc circuit may malfunction because it does not generate an internal reset signal. 2. clock oscillation is stopped by the resonator due to low power supply voltage before the poc circuit generates the internal reset signal. in this case, malfunction may result when the power supply voltage is recovered after the oscillation is stopped. this type of phenomenon takes place because the poc circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. if, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. in most cases, normal operation will be resumed. 3. in order to prevent malfunction, be sure to input a low level to one or more of pins k i0 to k i3 when poc is released due to supply voltage rising (can be left open. when open, leave the pull-down resistor connected).
39 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 8.1 functions of poc circuit the poc circuit has the following functions: ?generates an internal reset signal when v dd v poc . ?cancels an internal reset signal when v dd > v poc . here, v dd : power supply voltage, v poc : poc detection voltage. notes 1. actually, oscillation stabilization wait time must elapse before the circuit is switched to operation mode. the oscillation stabilization wait time is about 534/f x to 918/f x (when about 134 to 230 s; @ f x = 4 mhz). 2. for the poc circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the v poc for the period of 1 ms or more. therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect. 3. the poc detection voltage (v poc ) varies between approximately 1.7 to 1.9 v; thus, the reset may be canceled at a power supply voltage smaller than the guaranteed range (v dd = 1.9 to 3.6 v). however, as long as the conditions for operating the poc circuit are met, the actual lowest operating power supply voltage becomes lower than the poc detection voltage. therefore, there is no malfunction occurring due to a shortage of power supply voltage. however, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to cautions 3 in 8 poc circuit ). 8.2 oscillation check at low supply voltage a reliable reset operation can be expected of the poc circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the poc detection voltage). whether this condition is met or not can be checked by measuring the oscillation status in a product that actually includes a poc circuit, as follows. <1> connect a storage oscilloscope to the x out pin so that the oscillation status can be measured. <2> connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage v dd from 0 v (making sure to avoid v dd > 3.6v). at first (during v dd < approx. 1.7 v), the x out pin is 0 v regardless of the v dd . however, at the point that v dd reaches the poc detection voltage (v poc = 1.8 v (typ.)), the voltage of the x out pin jumps to about 0.5v dd . maintain this power supply voltage for a while to measure the waveform of the x out pin. if by any chance the oscillation start voltage of the resonator is lower than the poc detection voltage, the growing oscillation of the x out pin can be confirmed within several ms after the v dd has reached the v poc . v dd 3.6 v 1.9 v v poc approx. 1.7 v 0 v internal reset signal reset operating ambient temperature t a = ?40 to + 85 c clock frequency f x = 3.5 to 4.5 mhz poc detection voltage v poc = 1.8 v (typ.) note 3 t operation mode reset note 2 note 1
40 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 9. system clock oscillator ( pd6p8, 6p8a) the system clock oscillator consists of oscillators for ceramic resonators (f x = 3.5 to 4.5 mhz). figure 9-1. system clock the system clock oscillator stops oscillating when a reset is applied or in stop mode. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as gnd. do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. x out x in gnd ceramic resonator
41 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10. instruction set 10.1 machine language output by assembler the bit length of the machine language of this product is 10 bits per word. however, the machine language that is output by the assembler is extended to 16 bits per word. as shown in the example below, the extension is made by inserting 3-bit extended bits (111) in two locations. figure 10-1. example of assembler output (10 bits extended to 16 bits) <1> in the case of ?nl a, @r0h 1 1 1010 1 0000 1010 1 0000 111 111 extended bits extended bits = faf0 <2> in the case of ?ut p0, #data8 0 0 0110 1 1000 0110 1 1000 111 111 extended bits extended bits = e6f8
42 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10.2 circuit symbol description a: accumulator asr: address stack register addr: program memory address cy: carry flag data4: 4-bit immediate data data8: 8-bit immediate data data10: 10-bit immediate data f: status flag m0: modulo register for setting the low-level period m00: modulo register for setting the low-level period (lower 4 bits) m01: modulo register for setting the low-level period (higher 4 bits) m1: modulo register for setting the high-level period m10: modulo register for setting the high-level period (lower 4 bits) m11: modulo register for setting the high-level period (higher 4 bits) pc: program counter pn: port register pair (n = 0, 1, 3, 4) p0n: port register (lower 4 bits) p1n: port register (higher 4 bits) romn: bit n of the program memory? (n = 0 to 9) rn: register pair r0n: data memory (general-purpose register; n = 0 to f) r1n: data memory (general-purpose register; n = 0 to f) sp: stack pointer t: timer register t0: timer register (lower 4 bits) t1: timer register (higher 4 bits) ( ): content addressed with
43 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10.3 mnemonic to/from machine language (assembler output) contrast table accumulator operation instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle anl a, r0n fben (a) (a) (rmn) m = 0, 1 n = 0 to f 1 1 a, r1n faen cy a 3 ?rmn 3 a, @r0h faf0 (a) (a) ((p13), (r0)) 7-4 cy a 3 ?rom 7 a, @r0l fbf0 (a) (a) ((p13), (r0)) 3-0 cy a 3 ?rom 3 a, #data4 fbf1 data4 (a) (a) data4 2 cy a 3 ?data4 3 orl a, r0n fden (a) (a) (rmn) m = 0, 1 n = 0 to f 1 a, r1n fcen cy 0 a, @r0h fcf0 (a) (a) ((p13), (r0)) 7-4 cy 0 a, @r0l fdf0 (a) (a) ((p13), (r0)) 3-0 cy 0 a, #data4 fdf1 data4 (a) (a) data4 2 cy 0 xrl a, r0n f5en (a) (a) (rmn) m = 0, 1 n = 0 to f 1 a, r1n f4en cy a 3 ?rmn 3 a, @r0h f4f0 (a) (a) ((p13), (r0)) 7-4 cy a 3 ?rom 7 a, @r0l f5f0 (a) (a) ((p13), (r0)) 3-0 cy a 3 ?rom 3 a, #data4 f5f1 data4 (a) (a) data4 2 cy a 3 ?data4 3 inc a f4f3 (a) (a) + 1 1 if (a) = 0 cy 1 else cy 1 rl a fcf3 (a n+1 ) (a n ), (a 0 ) (a 3 ) cy a 3 rlz a fef3 if a = 0 reset else (a n+1 ) (a n ), (a 0 ) (a 3 ) cy a 3
44 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds i/o instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle in a, p0n fff8 + n (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 1 1 a, p1n fef8 + n cy 0 out p0n, a e5f8 + n (pmn) (a) m = 0, 1 n = 0, 1, 3, 4 p1n, a e4f8 + n anl a, p0n fbf8 + n (a) (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 a, p1n faf8 + n cy a 3 ?pmn 3 orl a, p0n fdf8 + n (a) (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 a, p1n fcf8 + n cy 0 xrl a, p0n f5f8 + n (a) (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 a, p1n f4f8 + n cy a 3 ?pmn 3 mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle out pn, #data8 e6f8 + n data8 (pn) data8 n = 0, 1, 3, 4 2 1 remark pn: p1n to p0n are dealt with in pairs. data transfer instruction mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov a, r0n ffen (a) (rmn) m = 0, 1 n = 0 to f 1 1 a, r1n feen cy 0 a, @r0h fef0 (a) ((p13), (r0)) 7-4 cy 0 a, @r0l fff0 (a) ((p13), (r0)) 3-0 cy 0 a, #data4 fff1 data4 (a) data4 2 cy 0 r0n, a e5en (rmn) (a) m = 0, 1 n = 0 to f 1 r1n, a e4en mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov rn , #data8 e6en data8 (r1n to r0n) data8 n = 0 to f 2 1 rn, @r0 e7en (r1n to r0n) ((p13), (r0))n = 1 to f 1 remark rn: r1n to r0n are handled in pairs.
45 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds branch instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle jmp addr (page 0) e8f1 addr pc addr 2 1 addr (page 1) e9f1 addr addr (page 2) e8f4 addr addr (page 3) e9f4 addr jc addr (page 0) ecf1 addr if cy = 1 pc addr addr (page 1) eaf1 addr else pc pc + 2 addr (page 2) ecf4 addr addr (page 3) eaf4 addr jnc addr (page 0) edf1 addr if cy = 0 pc addr addr (page 1) ebf1 addr else pc pc + 2 addr (page 2) edf4 addr addr (page 3) ebf4 addr jf addr (page 0) eef1 addr if f = 1 pc addr addr (page 1) f0f1 addr else pc pc + 2 addr (page 2) eef4 addr addr (page 3) f0f4 addr jnf addr (page 0) eff1 addr if f = 0 pc addr addr (page 1) f1f1 addr else pc pc + 2 addr (page 2) eff4 addr addr (page 3) f1f4 addr caution 0 and 4, which refer to page0 and 4, are not written when describing mnemonics. subroutine instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle call addr (page 0) e6f2 e8f1 addr sp sp + 1, asr pc, pc addr 3 2 addr (page 1) e6f2 e9f1 addr addr (page 2) e6f2 e8f4 addr addr (page 3) e6f2 e9f4 addr ret e8f2 pc asr, sp sp ?1 1 1 caution 0 and 4, which refer to page0 and 4, are not written when describing mnemonics.
46 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds timer operation instructions mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov a, t0 ffff (a) (tn) n = 0, 1 1 1 a, t1 feff cy 0 a, m00 fff6 (a) (m0n) n = 0, 1 a, m01 fef6 cy 0 a, m10 fff7 (a) (m1n) n = 0, 1 a, m11 fef7 cy 0 t0, a e5ff (tn) (a) n = 0, 1 t1, a f4ff (t) n 0 m00, a e5f6 (m0n) (a) n = 0, 1 m01, a e4f6 cy 0 m10, a e5f7 (m1n) (a) n = 0, 1 m11, a e4f7 cy 0 mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle mov t, #data10 e6ff data10 (t) data10 2 1 m0, #data10 e6f6 data10 (m0) data10 m1, #data10 e6f7 data10 (m1) data10 t, @r0 f4ff (t) ((p13), (r0)) 1 m0, @r0 e7f6 (m0) ((p13), (r0)) m1, @r0 e7f7 (m1) ((p13), (r0)) others mnemonic operand instruction code operation instruction instruction 1st word 2nd word 3rd word length cycle halt #data4 e2f1 data4 standby mode 2 1 stts #data4 e3f1 data4 if statuses match f 1 else f 0 r0n e3en if statuses match f 11 else f 0n = 0 to f scaf faf3 if a = 0fh cy 1 else cy 0 nop e0e0 pc pc + 1
47 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10.4 accumulator manipulation instructions anl a, r0n anl a, r1n <1> instruction code: 1 101r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) (a) (rmn) m = 0, 1 n = 0 to f cy a 3 ?rmn 3 the accumulator contents and the register rmn contents are anded and the results are entered in the accumulator. anl a, @r0h anl a, @r0l <1> instruction code: 1 1010/110000 <2> cycle count: 1 <3> function: (a) (a) ((p13), (r0)) 7-4 (in the case of anl a, @r0h) cy a 3 ?rom 7 (a) (a) ((p13), (r0)) 3-0 (in the case of anl a, @r0l) cy a 3 ?rom 3 the accumulator contents and the program memory contents specified by the control register p13 and register pair r 10 to r 00 are anded and the results are entered in the accumulator. if h is specified, b 7 , b 6 , b 5 and b 4 take effect. if l is specified, b 3 , b 2 , b 1 and b 0 take effect. program memory (rom) organization anl a, #data4 <1> instruction code: 1 101110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) (a) data4 cy a 3 ?data4 3 the accumulator contents and the immediate data are anded and the results are entered in the accumulator. b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 h l valid bits at the time of accumulator manipulation
48 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds orl a, r0n orl a, r1n <1> instruction code: 1 110r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) (a) (rmn) m = 0, 1 n = 0 to f cy 0 the accumulator contents and the register rmn contents are ored and the results are entered in the accumulator. orl a, @r0h orl a, @r0l <1> instruction code: 1 1100/110000 <2> cycle count: 1 <3> function: (a) (a) (p13), (r0)) 7-4 (in the case of orl a, @r0h) (a) (a) (p13), (r0)) 3-0 (in the case of orl a, @r0l) cy 0 the accumulator contents and the program memory contents specified by the control register p13 and register pair r 10 -r 00 are ored and the results are entered in the accumulator. if h is specified, b 7 , b 6 , b 5 and b 4 take effect. if l is specified, b 3 , b 2 , b 1 and b 0 take effect. orl a, #data4 <1> instruction code: 1 110110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) (a) data4 cy 0 the accumulator contents and the immediate data are exclusive-ored and the results are entered in the accumulator. xrl a, r0n xrl a, r1n <1> instruction code: 1 010r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) (a) (rmn) m = 0, 1 n = 0 to f cy a 3 ?rmn 3 the accumulator contents and the register rmn contents are ored and the results are entered in the accumulator.
49 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds xrl a, @r0h xrl a, @r0l <1> instruction code: 1 0100/110000 <2> cycle count: 1 <3> function: (a) (a) (p13), (r0)) 7-4 (in the case of xrl a, @r0h) cy a 3 ?rom 7 (a) (a) (p13), (r0)) 3-0 (in the case of xrl a, @r0l) cy a 3 ?rom 3 the accumulator contents and the program memory contents specified by the control register p13 and register pair r 10 -r 00 are exclusive-ored and the results are entered in the accumulator. if h is specified, b 7 , b 6 , b 5 , and b 4 take effect. if l is specified, b 3 , b 2 , b 1 , and b 0 take effect. xrl a, #data4 <1> instruction code: 1 010110001 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) (a) data4 cy a 3 ?data4 3 the accumulator contents and the immediate data are exclusive-ored and the results are entered in the accumulator. inc a <1> instruction code: 1 010010011 <2> cycle count: 1 <3> function: (a) (a) + 1 if a = 0 cy 1 else cy 0 the accumulator contents are incremented (+1). rl a <1> instruction code: 1 110010011 <2> cycle count: 1 <3> function: (a n + 1 ) (an), (a 0 ) (a 3 ) cy a 3 the accumulator contents are rotated anticlockwise bit by bit. rlz a <1> instruction code: 1 111010011 <2> cycle count: 1 <3> function: if a = 0 reset else (a n + 1 ) (an), (a 0 ) (a 3 ) cy a 3 the accumulator contents are rotated anticlockwise bit by bit. if a = 0h at the time of command execution, an internal reset takes effect.
50 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10.5 i/o instructions in a, p0n in a, p1n <1> instruction code: 1 111p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy 0 the port pmn data is loaded (read) onto the accumulator. out p0n, a out p1n, a <1> instruction code: 0 010p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (pmn) (a) m = 0, 1 n = 0, 1, 3, 4 the accumulator contents are transferred to port pmn to be latched. anl a, p0n anl a, p1n <1> instruction code: 1 101p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy a 3 ?pmn the accumulator contents and the port pmn contents are anded and the results are entered in the accumulator. orl a, p0n orl a, p1n <1> instruction code: 1 110p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy 0 the accumulator contents and the port pmn contents are ored and the results are entered in the accumulator. xrl a, p0n xrl a, p1n <1> instruction code: 1 010p 4 11p 2 p 1 p 0 <2> cycle count: 1 <3> function: (a) (a) (pmn) m = 0, 1 n = 0, 1, 3, 4 cy a 3 ?pmn the accumulator contents and the port pmn contents are exclusive-ored and the results are entered in the accumulator.
51 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds out pn, #data8 <1> instruction code: 0 011011p 2 p 1 p 0 : 0d 7 d 6 d 5 d 4 0d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (pn) data8 n = 0, 1, 3, 4 the immediate data is transferred to port pn. in this case, port pn refers to p 1n to p 0n operating in pairs. 10.6 data transfer instructions mov a, r0n mov a, r1n <1> instruction code: 1 111r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (a) (rmn) m = 0, 1 n = 0 to f cy 0 the register rmn contents are transferred to the accumulator. mov a, @r0h <1> instruction code: 1 111010000 <2> cycle count: 1 <3> function: (a) ((p13), (r0)) 7-4 cy 0 the higher 4 bits (b 7 b 6 b 5 b 4 ) of the program memory specified by control register p13 and register pair r 10 -r 00 are transferred to the accumulator. b 9 is ignored. mov a, @r0l <1> instruction code: 1 111110000 <2> cycle count: 1 <3> function: (a) ((p13), (r0)) 3-0 cy 0 the lower 4 bits (b 3 b 2 b 1 b 0 ) of the program memory specified by control register p13 and register pair r 10 to r 00 are transferred to the accumulator. b 8 is ignored. ? program memory (rom) contents b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 @r 0 h@r 0 l mov a, #data4 <1> instruction code: 1 111110001 : 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (a) data4 cy 0 the immediate data is transferred to the accumulator.
52 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds mov r0n, a mov r1n, a <1> instruction code: 0 010r 4 0r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (rmn) (a) m = 0, 1 n = 0 to f the accumulator contents are transferred to register rmn. mov rn, #data8 <1> instruction code: 0 01100r 3 r 2 r 1 r 0 : 0 d 7 d 6 d 5 d 4 0d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: (r1n-r0n) data8 n = 0 to f the immediate data is transferred to the register. using this instruction, registers operate as register pairs. the pair combinations are as follows: r 0 : r 10 - r 00 r 1 : r 11 - r 01 : r e : r 1e - r 0e r f : r 1f - r 0f lower column higher column mov rn, @r0 <1> instruction code: 0 01110r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: (r1n-r0n) ((p13), r0)) n = 1 to f the program memory contents specified by control register p13 and register pair r 10 to r 00 are transferred to register pair r1n to r0n. the program memory consists of 10 bits and has the following state after the transfer to the register. b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 @r0 r1n r0n program memory the higher 2 to 4 bits of the program memory address are specified by the control register (p13).
53 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10.7 branch instructions the program memory consists of pages in steps of 1k (000h to 3ffh). however, as the assembler automatically performs page optimization, it is unnecessary to designate pages. the pages allowed for each product are as follows. pd6p8, 6p8a, 6p8b (rom: 2k steps): pages 0, 1 jmp addr <1> instruction code: page 0 0100010001 ; page 1 0100110001 page 2 0100010100 ; page 3 0100110100 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: pc addr the 10 bits (pc 9-0 ) of the program counter are replaced directly by the specified address addr (a 9 to a 0 ). jc addr <1> instruction code: page 0 0110010001 ; page 1 0101010001 page 2 0110010100 ; page 3 0101010100 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if cy = 1 pc addr else pc pc + 2 if the carry flag cy is set (to 1), a jump is made to the address specified by addr (a 9 to a 0 ). jnc addr <1> instruction code: page 0 0110110001 ; page 1 0101110001 page 2 0110110100 ; page 3 0101110100 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if cy = 0 pc addr else pc pc + 2 if the carry flag cy is cleared (to 0), a jump is made to the address specified by addr (a9 to a0). jf addr <1> instruction code: page 0 0111010001 ; page 1 1000010001 page 2 0111010100 ; page 3 1000010100 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if f = 1 pc addr else pc pc + 2 if the status flag f is set (to 1), a jump is made to the address specified by addr (a 9 to a 0 ).
54 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds jnf addr <1> instruction code: page 0 0111110001 ; page 1 1000110001 page 2 0111110100 ; page 3 1000110100 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 1 <3> function: if f = 0 pc addr else pc pc + 2 if the status flag f is cleared (to 0), a jump is made to the address specified by addr (a 9 to a 0 ). 10.8 subroutine instructions the program memory consists of pages in steps of 1k (000h to 3ffh). however, as the assembler automatically performs page optimization, it is unnecessary to designate pages. the pages allowed for each product are as follows. pd6p8, 6p8a, 6p8b (rom: 2k steps): pages 0, 1 call addr <1> instruction code: 0 011010010 page 0 0100010001 ; page 1 0100110001 page 2 0100010100 ; page 3 0100110100 a 9 a 7 a 6 a 5 a 4 a 8 a 3 a 2 a 1 a 0 <2> cycle count: 2 <3> function: sp sp + 1 asr pc pc addr increments (+1) the stack pointer value and saves the program counter value in the address stack register. then, enters the address specified by the operand addr (a 9 to a 0 ) into the program counter. if a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. ret <1> instruction code: 0 100010010 <2> cycle count: 1 <3> function: pc asr sp sp ?1 restores the value saved in the address stack register to the program counter. then, decrements (?) the stack pointer. if a borrow is generated when the stack pointer value is decremented (?), an internal reset takes effect.
55 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 10.9 timer operation instructions mov a, t0 mov a, t1 <1> instruction code: 1111 0/1 1 1 1 1 1 <2> cycle count: 1 <3> function: (a) (tn) n = 0, 1 cy 0 the timer register tn contents are transferred to the accumulator. t1 corresponds to (t 9 , t 8 , t 7 , t 6 ); t0 corresponds to (t 5 , t 4 , t 3 , t 2 ). t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 can be set with t1 t0 mov t, #data10 mov t, @r0 t mov a, m00 mov a, m01 <1> instruction code: 1111 0/1 1 0 1 1 0 <2> cycle count: 1 <3> function: (a) (m0n) n = 0, 1 cy 0 the modulo register m0n contents are transferred to the accumulator. m01 corresponds to (t 9 , t 8 , t 7 , t 6 ); m00 corresponds to (t 5 , t 4 , t 3 , t 2 ). t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 can be set with m01 m00 mov m0, #data10 mov m0, @r0 m0
56 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds mov a, m10 mov a, m11 <1> instruction code: 1111 0/1 1 0 1 1 1 <2> cycle count: 1 <3> function: (a) (m1n) n = 0, 1 cy 0 the modulo register m1n contents are transferred to the accumulator. m11 corresponds to (t 9 , t 8 , t 7 , t 6 ); m10 corresponds to (t 5 , t 4 , t 3 , t 2 ). t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 can be set with m11 m10 mov m1, #data10 mov m1, @r0 m1 mov t0, a mov t1, a <1> instruction code: 0010 0/1 1 1 1 1 1 <2> cycle count: 1 <3> function: (tn) (a) n = 0, 1 the accumulator contents are transferred to the timer register tn. t1 corresponds to (t 9 , t 8 , t 7 , t 6 ); t0 corresponds to (t 5 , t 4 , t 3 , t 2 ). after executing this instruction, if data is transferred to t1, t 1 becomes 0; if data is transferred to t0, t 0 becomes 0. mov m00, a mov m01, a <1> instruction code: 0010 0/1 1 0 1 1 0 <2> cycle count: 1 <3> function: (m0n) (a) n = 0, 1 cy 0 the accumulator contents are transferred to the modulo register m0n. m01 corresponds to (t 9 , t 8 , t 7 , t 6 ); m00 corresponds to (t 5 , t 4 , t 3 , t 2 ). after executing this instruction, if data is transferred to m01, t 1 becomes 0; if data is transferred to m00, t 0 becomes 0. mov m10, a mov m11, a <1> instruction code: 0010 0/1 1 0 1 1 1 <2> cycle count: 1 <3> function: (m1n) (a) n = 0, 1 cy 0 the accumulator contents are transferred to the modulo register m1n. m11 corresponds to (t 9 , t 8 , t 7 , t 6 ); m10 corresponds to (t 5 , t 4 , t 3 , t 2 ). after executing this instruction, if data is transferred to m11, t 1 becomes 0; if data is transferred to m10, t 0 becomes 0.
57 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds mov t, #data10 <1> instruction code: 0 011011111 t 1 t 9 t 8 t 7 t 6 t 0 t 5 t 4 t 3 t 2 <2> cycle count: 1 <3> function: (t) data10 the immediate data is transferred to the timer register t (t 9 to t 0 ). remark the timer time is set as follows. (set value + 1) 64/f x ?4/f x mov m0, #data10 <1> instruction code: 0 011010110 t 1 t 9 t 8 t 7 t 6 t 0 t 5 t 4 t 3 t 2 <2> cycle count: 1 <3> function: (m0) data10 the immediate data is transferred to the modulo register m0 (t 9 to t 0 ). mov m1, #data10 <1> instruction code: 0 011010111 t 1 t 9 t 8 t 7 t 6 t 0 t 5 t 4 t 3 t 2 <2> cycle count: 1 <3> function: (m1) data10 the immediate data is transferred to the modulo register m1 (t 9 to t 0 ). mov t, @r0 <1> instruction code: 0 011111111 <2> cycle count: 1 <3> function: (t) ((p13), (r0)) transfers the program memory contents to the timer register t (t 9 to t 0 ) specified by the control register p13 and the register pair r 10 to r 00 . the program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 t1 t0 t 1 t 0 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 @r 0 program memory timer t the higher 2 to 4 bits of the program memory address are specified by the control register (p13). caution when setting a timer value in the program memory, be sure to use the dt quasi-directive.
58 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds mov m0, @r0 <1> instruction code: 0 011110110 <2> cycle count: 1 <3> function: (m0) ((p13), (r0)) transfers the program memory contents to the modulo register m0 (t 9 to t 0 ) specified by the control register p13 and the register pair r 10 to r 00 . the program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 m01 m00 t 1 t 0 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 @r 0 program memory modulo register m0 the higher 2 to 4 bits of the program memory address are specified by the control register (p13). caution when setting a timer value in the program memory, be sure to use the dt quasi-directive. mov m1, @r0 <1> instruction code: 0 011110111 <2> cycle count: 1 <3> function: (m1) ((p13), (r0)) transfers the program memory contents to the modulo register m1 (t 9 to t 0 ) specified by the control register p13 and the register pair r 10 to r 00 . the program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 m11 m10 t 1 t 0 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 @r 0 program memory modulo register m1 the higher 2 to 4 bits of the program memory address are specified by the control register (p13). caution when setting a timer value in the program memory, be sure to use the dt quasi-directive. 10.10 others halt #data4 <1> instruction code: 0 001010001 : 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: standby mode places the cpu in standby mode. the condition for having the standby mode (halt/stop mode) canceled is specified by the immediate data.
59 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds stts r0n <1> instruction code: 0 00110r 3 r 2 r 1 r 0 <2> cycle count: 1 <3> function: if statuses match f 1 else f 0n = 0 to f compares the s 0 , s 1 , k i/o , k i , and timer statuses with the register r 0n contents. if at least one of the statuses matches the bits that have been set, the status flag f is set (to 1). if none of them match, the status flag f is cleared (to 0). stts #data4 <1> instruction code: 0 001110001 : 0 00000d 3 d 2 d 1 d 0 <2> cycle count: 1 <3> function: if statuses match f 1 else f 0 compares the s 0 , s 1 , s 2 , k i/o , k i , and timer statuses with the immediate data contents. if at least one of the statuses matches the bits that have been set, the status flag f is set (to 1). if none of them match, the status flag f is cleared (to 0). scaf (set carry if a cc = f h ) <1> instruction code: 1 101010011 <2> cycle count: 1 <3> function: if a = 0fh cy 1 else cy 0 sets the carry flag cy (to 1) if the accumulator contents are fh. the accumulator values after executing the scaf instruction are as follows: accumulator value carry flag before execution after execution 0 0000 0 (clear) 01 0001 0 (clear) 011 0011 0 (clear) 0111 0111 0 (clear) 1111 1111 1 (set) remark : don? care nop <1> instruction code: 0 000000000 <2> cycle count: 1 <3> function: pc pc + 1 no operation
60 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 11. assembler reserved words 11.1 mask option directives when creating a program in the pd6p8, 6p8a, 6p8b, it is necessary to use a mask option quasi-directive in the assembler? source program. to create a program for the pd6p8, 6p8a, or 6p8b, a mask option pseudo instruction must be used in the assembler source program, but since the pd6p8, 6p8a, or 6p8b does not have a mask option, describe nousecap. 11.1.1 option and endop quasi-directives the quasi-directives from the option quasi-directive down to the endop quasi-directive are called the mask option definition block. the format of the mask option definition block is as follows: format symbol field mnemonic field operand field comment field [label:] option [; comment] : : endop 11.1.2 mask option definition quasi-directives the quasi-directives that can be used in the mask option definition block are listed in table 10-1. the mask option definition can only be specified as follows. be sure to specify the following quasi-directives. example symbol field mnemonic field operand field comment field option nousecap ; capacitor for oscillation endop ; not incorporated table 11-1. mask option definition directives name mask option definition quasi-directive pro file address value data value cap nousecap 2043h 00 (capacitor for oscillation not incorporated)
61 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 12.writing and verifying one-time prom (program memory) ( pd6p8) the program memory of the pd6p8 is a one-time prom of 2026 10 bits. to write or verify this one-time prom, the pins shown in table 5-1 are used. note that no address input pin is used. instead, the address is updated by using the clock input from the clk pin. table 12-1. pins used to write/verify program memory pin name function v pp supplies voltage when writing/verifying program memory. apply +10.5 v to this pin. v dd power supply. supply +3 v to this pin when writing/verifying program memory. clk inputs clock to update address when writing/verifying program memory. by inputting a pulse four times to the clk pin, the address of the program memory is updated. md 0 to md 3 input to select the operation mode when writing/verifying program memory. d 0 to d 7 inputs/outputs 8-bit data when writing/verifying program memory. x in , x out clock necessary for writing program memory. connect a 4 mhz ceramic resonator to this pin. 12.1 operating mode when writing/verifying program memory the pd6p8 is set in the program memory write/verify mode when +10.5 v is applied to the v pp pin after the pd6p8 has been in the reset status (v dd = 3 v, v pp = 0 v) for a specific time. in this mode, the operating modes shown in table 5-2 can be set by setting the md 0 through md 3 pins. connect all the pins other than those shown in table 5-1 to gnd via pull-down resistors. table 12-2. setting operating mode setting of operating mode operating mode v pp v dd md 0 md 1 md 2 md 3 +10.5 v +3 v h l h l clear program memory address to 0 l hhh write mode ll hh verify mode h hh program inhibit mode : don? care (l or h)
62 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 12.2 program memory writing procedure the program memory is written at high speed by the following procedure. (1) pull down the pins not used to gnd via a resistor. keep the clk pin low. (2) supply 3 v to the v dd pin. keep the v pp pin low. (3) supply 3 v to the v pp pin after waiting for 10 s. (4) wait for 2 ms until oscillation of the ceramic resonator connected across the x in and x out pins stabilizes. (5) set the program memory address 0 clear mode by using the mode setting pins. (6) supply 10.5 v to v pp . (7) set the program inhibit mode. input a pulse to the clk pin four times. (8) write data to the program memory in the 100 s write mode. (9) set the program inhibit mode. (10) set the verify mode. if the data have been written to the program memory, proceed to (11). if not, repeat steps (8) through (10). (11) additional writing of (number of times of writing in (8) through (10): x) 100 s. (12) set the program inhibit mode. (13) input a pulse to the clk pin four times to update the program memory address (+1). (14) repeat steps (8) through (13) up to the last address. (15) set the 0 clear mode of the program memory address. (16) change the voltages on the v pp pin to 3 v. (17) turn off the power. the following figure illustrates steps (2) through (13) above. v pp v dd gnd v dd gnd clk v pp d 0 to d 7 md 0 md 1 md 2 md 3 v dd repeated x time reset oscillation stabilization wait time write verify additional write address increment data input hi-z hi-z hi-z data output data input hi-z
63 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 12.3 program memory reading procedure (1) pull down the pins not used to gnd via a resistor. keep the clk pin low. (2) supply 3 v to the v dd pin. keep the v pp pin low. (3) supply 3 v to the v pp pin after waiting for 10 s. (4) wait for 2 ms until oscillation of the ceramic resonator connected across the x in and x out pins stabilizes. (5) set the program memory address 0 clear mode by using the mode setting pins. (6) supply 10.5 v to v pp . (7) set the program inhibit mode. input a pulse to the clk pin four times. (8) set the verify mode. data of each address is output sequentially each time the clock pulse is input to the clk pin four times. (9) set the program inhibit mode. (10) set the program memory address 0 clear mode. (11) change the voltage on the v pp pin to 3 v. (12) turn off the power. the following figure illustrates steps (2) through (10) above. v pp v dd gnd v dd gnd clk v pp v dd d 0 to d 7 md 0 md 1 md 2 md 3 reset oscillation stabilization wait time hi-z hi-z data output data output "l"
64 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 13.writing and verification of one-time prom (program memory) ( pD6P8A, 6p8b) the program memory built into the pD6P8A and 6p8b is a one-time prom of 2026 10 bits. writing or verification of this one-time prom is performed using the pins listed in table 13-1, and a 5-bit instruction and 5-bit data via serial communication. the assembler output has an 8-bit configuration, so mask the higher three bits and program the lower five bits. table 13-1. pins used during program memory writing/verification pin no. symbol function i/o 2s o serial data output during program memory verification output 3 sclk clock input during program memory writing or verification input 4s i serial data input during program memory writing input 6v dd power supply supply +3 v to this pin during program memory writing or verification. 7x out clock required during program memory writing or verification. connect a 8x in 4 mhz ceramic resonator to these pins. input 9 gnd gnd 10 v pp voltage application pin during program memory writing or verification. apply +10.5 v to this pin. 13.1 initialization when a high voltage (10.5 v) is supplied to v pp , the programming mode is set after about 1 ms. in the programming mode, pins not used for programming are pulled down internally, so leave them open. s1/led is set to output mode (h) when 3 v is supplied to v dd and v pp . when a high voltage (10.5 v) is supplied to v pp , the input mode is set after about 1 ms. serial communication is performed in 5-bit units, starting from the msb.
65 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds perform initialization according to the following procedure. (1) supply 3 v to the v dd pin. set the v pp pin to low level. (2) supply 3 v (same potential as v dd ) to the v pp pin after waiting for 10 s. (3) wait for 2 ms until oscillation stabilizes. (4) supply 10.5 v to the v pp pin. (5) wait for 1 ms until oscillation stabilizes. (6) transmit the pcreset instruction from the programmer. (7) transmit the ssverify instruction from the programmer for silicon signature verification. 1 v pp (10.5 v) v dd v pp v dd gnd v dd gnd 2345 6 7 10 s 13.2 serial communication format instruction data all instructions consist of a 5-bit instruction and 5-bit data. the data from the programmer is latched at the rising edge of sclk. the pD6P8A and 6p8b output data is output at the falling edge of sclk. instruction format 43210 md4 md3 md2 md1 md0 md4 to md0 instruction function 05 reset clearing the program memory address to 0 0c verify verify mode 0e program write mode 11 increment incrementing of the program memory address 08 signature verify silicon signature verify mode 01 inhibit program inhibit mode
66 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 13.3 writing of program memory ci4 v pp sclk si program command program data so ci3 ci2 ci1 0111 ci4 ci3 ci2 ci1 ci0 0 ci0 13.4 reading of program memory ci4 v pp sclk si so ci3 ci2 ci1 0110 do4 do3 do2 do1 ci0 0 do1 v erify command read data
67 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 14. electrical specifications ( pd6p8) absolute maximum ratings (t a = +25 c) parameter symbol conditions rating unit power supply voltage v dd ?.3 to +5.0 v v pp ?.3 to +11.0 v input voltage v i k i/o0 -k i/o7 , k i0 -k i3 , s 0 , s 1 , s 2 ?.3 to v dd + 0.3 v output voltage v o ?.3 to v dd + 0.3 v output current, high i oh note rem peak value ?0 ma rms ?0 ma led peak value ?.5 ma rms ? ma per k i/o0 -k i/o7 pin peak value ?3.5 ma rms ? ma total for led and k i/o0 -k i/o7 peak value ?8 ma pins rms ?2 ma output current, low i ol note rem peak value 7.5 ma rms 5 ma led peak value 7.5 ma rms 5 ma operating ambient t a ?0 to +85 c temperature storage temperature t stg ?5 to +150 c note calculate the rms with: [rms] = [peak value] duty. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended power supply voltage range (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit power supply voltage v dd f x = 3.5 to 4.5 mhz 1.9 3.0 3.6 v
68 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) item symbol conditions min. typ. max. unit input voltage, high v ih1 k i/o0 -k i/o7 0.7v dd v dd v v ih2 k i0 -k i3 , s 0 , s 1 , s 2 0.65v dd v dd v input voltage, low v il1 k i/o0 -k i/o7 0 0.3v dd v v il2 k i0 -k i3 , s 0 , s 1 , s 2 0 0.15v dd v input leakage current, i lih1 k i0 -k i3 3 a high v i = v dd , pull-down resistor not incorporated i lih2 s 0 , s 1 , s 2 3 a v i = v dd , pull-down resistor not incorporated input leakage current, i lil1 k i0 -k i3 v i = 0 v 3 a low i lil2 k i/o0 -k i/o7 v i = 0 v 3 a i lil3 s 0 , s 1 , s 2 v i = 0 v 3 a output voltage, high v oh1 rem, led, k i/o0 -k i/o7 i oh = ?.3 ma 0.8v dd v output voltage, low v ol1 rem, led i ol = 0.3 ma 0.3 v v ol2 k i/o0 -k i/o7 i ol = 15 a 0.4 v output current, high i oh1 rem v dd = 3.0 v, v oh = 1.0 v 5 9 ma i oh2 k i/o0 -k i/o7 v dd = 3.0 v, v oh = 2.2 v ?.5 ? ma output current, low i ol1 k i/o0 -k i/o7 v dd = 3.0 v, v ol = 0.4 v 30 70 a v dd = 3.0 v, v ol = 2.2 v 100 220 a o n-chip pull-down resistor r 1 k i0 -k i3 , s 0 , s 1 , s 2 75 150 300 k ? r 2 k i/o0 -k i/o7 130 250 500 k ? data retention power v ddor in stop mode 1.2 3.6 v supply voltage ram retention detection v id 1.8 1.9 v voltage supply current i dd1 operation f x = 4.0 mhz, v dd = 3 v 10% 1.1 2.2 ma mode i dd2 halt mode f x = 4.0 mhz, v dd = 3 v 10% 1.0 2.0 ma i dd3 stop mode v dd = 3 v 10% 2.2 9.5 a v dd = 3 v 10%, t a = 25 c 2.2 3.5 a
69 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x in x out c1 c2 ac characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) parameter symbol conditions min. typ. max. unit i nst ruc tio n execution time t cy 14 16 18.5 s k i0 -k i3 , s 0 , s 1 high-level t h 10 s width when releasing standby mode in halt mode 10 s in stop mode note s reset low-level width t rsl 10 s note 10 + 284/f x + oscillation growth time remark t cy = 64/f x (f x : system clock oscillation frequency) poc circuit (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit poc detection voltage note v poc 1.8 1.9 v note refers to the voltage with which the poc circuit releases an internal reset. if v poc < v dd , the internal reset is released. from the time of v poc v dd until the internal reset takes effect, lag of up to 1 ms occurs. when the period of v poc v dd lasts less than 1 ms, the internal reset may not take effect. system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) parameter symbol conditions min. typ. max. unit oscillation frequency f x 3.5 4.0 4.5 mhz (ceramic resonator) external circuit example
70 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds recommended oscillator constant ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended constant (pf) oscillation voltage range (v dd ) remark (mhz) c1 c2 min. max. murata mfg. cstcc3m50g56-r0 3.50 unnecessary (on-chip c type) 1.9 3.6 co., ltd. cstls3m50g56-b0 cstcc3m64g56-r0 3.64 cstls3m64g56-b0 cstcr4m00g55-r0 4.00 cstls4m00g56-b0 cstcr4m19g55-r0 4.19 cstls4m19g56-b0 cstcr4m50g55-r0 4.50 cstls4m50g56-b0 external circuit example caution these oscillator constants are reference values based on evaluation by the manufacturer of the resonator under a specific environment. if optimization of the oscillator characteristics is required for the actual application, apply to the resonator manufacturer for evaluation on the mounting circuit. the oscillation voltage and oscillation frequency only indicate the oscillator characteristics; the oscillator must be used within the ratings of the dc and ac characteristics specified under the internal operation conditions. remark the incorporation of the oscillation capacitor by a mask option is under evaluation. x in x out c1 c2
71 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds prom programming mode dc programming characteristics (t a = 25 c, v dd = 3.0 0.3 v, v pp = 10.5 0.3 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 other than clk 0.7v dd v dd v v ih2 clk v dd ?0.5 v dd v input voltage, low v il1 other than clk 0 0.3v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 a output voltage, high v oh i oh = ? ma v dd ?1.0 v output voltage, low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md 0 = v il , md 1 = v ih 30 ma cautions 1. keep v pp to within +11.0 v including overshoot. 2. apply v dd before v pp and turns it off after v pp .
72 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds ac programming characteristics (t a = 25 c, v dd = 3.0 0.3 v, v pp = 10.5 0.3 v) parameter symbol conditions min. typ. max. unit address setup time note 1 (to md 0 )t as 2 s md 1 setup time (to md 0 )t m1s 2 s data setup time (to md 0 )t ds 2 s address hold time note 1 (from md 0 )t ah 2 s data hold time (from md 0 )t dh 2 s delay time from md 0 to data output float t df 04 s v pp setup time (to md 3 )t vps 2 s v dd setup time (to md 3 )t vds 2 s initial program pulse width t pw 0.095 0.1 0.105 ms additional program pulse width t opw 0.095 2.1 ms md 0 setup time (to md 1 )t mos 2 s delay time from md 0 to data output t dv md0 = md1 = v il 4 s md 1 hold time (from md 0 )t m1h t m1h +t m1r 50 s2 s md 1 recovery time (to md 0 )t m1r 2 s program counter reset time t pcr 10 s clk input high-/low-level width t xh , t xl 0.125 s clk input frequency f x 4.19 mhz initial mode set time t i 2 s md 3 setup time (to md 1 )t m3s 2 s md 3 hold time (from md 1 )t m3h 2 s md 3 setup time (to md 0 )t m3sr when program memory is read 2 s delay time from address note 1 to data output t oad when program memory is read 4 s hold time from address note 1 to data output t had when program memory is read 04 s md 3 hold time (from md 0 )t m3hr when program memory is read 2 s delay time from md 3 to data output float t dfr when program memory is read 4 s reset setup time t res 10 s oscillation stabilization wait time note 2 t wait 2ms notes 1. the internal address signal is incremented at the falling edge of the third clock of clk. 2. connect a 4 mhz ceramic resonator between the x in and x out pins.
73 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds t m3sr t pcr t dv t dv t i t xl t dad t had t vps t xh t xl t xh t m3hr t dfr v pp v pp v dd gnd v dd v dd gnd clk d 0 -d 7 md 0 md 1 md 2 md 3 t res hi-z hi-z t wait data output "l" data output t res t vps t xh t xl t as t xh t xl t as t ah t dh t ds t opw t df t dv t mos t m1r t dh t ds t pw t i t m3h t m1h t m1s t pcr t m3s hi-z hi-z hi-z hi-z hi-z t wait v pp v dd gnd v dd gnd clk v pp d 0 to d 7 md 0 md 1 md 2 md 3 v dd data input data output data input data input program memory read timing program memory write timing
74 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 15. electrical specifications ( pD6P8A) absolute maximum ratings (t a = +25 c) parameter symbol conditions rating unit power supply voltage v dd ?.3 to +5.0 v v pp ?.3 to +11.0 v input voltage v i k i/o0 -k i/o7 , k i0 -k i3 , s 0 , s 1 , s 2 ?.3 to v dd + 0.3 v output voltage v o ?.3 to v dd + 0.3 v output current, high i oh note rem peak value ?0 ma rms ?0 ma led peak value ?.5 ma rms ? ma per k i/o0 -k i/o7 pin peak value ?3.5 ma rms ? ma total for led and k i/o0 -k i/o7 peak value ?8 ma pins rms ?2 ma output current, low i ol note rem peak value 7.5 ma rms 5 ma led peak value 7.5 ma rms 5 ma operating ambient t a ?0 to +85 c temperature storage temperature t stg ?5 to +150 c note calculate the rms with: [rms] = [peak value] duty. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended power supply voltage range (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit power supply voltage v dd f x = 3.5 to 4.5 mhz 1.9 3.0 3.6 v
75 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) item symbol conditions min. typ. max. unit input voltage, high v ih1 k i/o0 -k i/o7 0.7v dd v dd v v ih2 k i0 -k i3 , s 0 , s 1 , s 2 0.65v dd v dd v input voltage, low v il1 k i/o0 -k i/o7 0 0.3v dd v v il2 k i0 -k i3 , s 0 , s 1 , s 2 0 0.15v dd v input leakage current, i lih1 k i0 -k i3 3 a high v i = v dd , pull-down resistor not incorporated i lih2 s 0 , s 1 , s 2 3 a v i = v dd , pull-down resistor not incorporated input leakage current, i lil1 k i0 -k i3 v i = 0 v 3 a low i lil2 k i/o0 -k i/o7 v i = 0 v 3 a i lil3 s 0 , s 1 , s 2 v i = 0 v 3 a output voltage, high v oh1 rem, led, k i/o0 -k i/o7 i oh = ?.3 ma 0.8v dd v output voltage, low v ol1 rem, led i ol = 0.3 ma 0.3 v v ol2 k i/o0 -k i/o7 i ol = 15 a 0.4 v output current, high i oh1 rem v dd = 3.0 v, v oh = 1.0 v 5 9 ma i oh2 k i/o0 -k i/o7 v dd = 3.0 v, v oh = 2.2 v ?.5 ? ma output current, low i ol1 k i/o0 -k i/o7 v dd = 3.0 v, v ol = 0.4 v 30 70 a v dd = 3.0 v, v ol = 2.2 v 100 220 a o n-chip pull-down resistor r 1 k i0 -k i3 , s 0 , s 1 , s 2 75 150 300 k ? r 2 k i/o0 -k i/o7 130 250 500 k ? data retention power v ddor in stop mode 1.2 3.6 v supply voltage ram retention detection v id 1.6 1.7 v voltage supply current i dd1 operation f x = 4.0 mhz, v dd = 3 v 10% 0.7 1.4 ma mode i dd2 halt mode f x = 4.0 mhz, v dd = 3 v 10% 0.65 1.3 ma i dd3 stop mode v dd = 3 v 10% 2.2 9.5 a v dd = 3 v 10%, t a = 25 c 2.2 3.5 a
76 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x in x out c1 c2 ac characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) parameter symbol conditions min. typ. max. unit i nst ruc tio n execution time t cy 14 16 18.5 s k i0 -k i3 , s 0 , s 1 high-level t h 10 s width when releasing standby mode in halt mode 10 s in stop mode note s reset low-level width t rsl 10 s note 10 + 1024/f x + oscillation growth time remark t cy = 64/f x (f x : system clock oscillation frequency) poc circuit (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit poc detection voltage note v poc 1.8 1.9 v note refers to the voltage with which the poc circuit releases an internal reset. if v poc < v dd , the internal reset is released. from the time of v poc v dd until the internal reset takes effect, lag of up to 1 ms occurs. when the period of v poc v dd lasts less than 1 ms, the internal reset may not take effect. system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) parameter symbol conditions min. typ. max. unit oscillation frequency f x 3.5 4.0 4.5 mhz (ceramic resonator) external circuit example
77 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds prom programming mode dc programming characteristics (t a = 25 c, v dd = 3.0 0.3 v, v pp = 10.5 0.3 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 other than sclk 0.7v dd v dd v v ih2 sclk v dd ?0.5 v dd v input voltage, low v il1 other than sclk 0 0.3v dd v v il2 sclk 0 0.4 v input leakage current i li v in = v il or v ih 10 a output voltage, high v oh i oh = ? ma v dd ?1.0 v output voltage, low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 2ma v pp supply current i pp 0.3 ma cautions 1. keep v pp to within +11.0 v including overshoot. 2. apply v dd before v pp and turns it off after v pp . ac programming characteristics (t a = 25 c, v dd = 3.0 0.3 v, v pp = 10.5 0.3 v) parameter symbol conditions min. typ. max. unit reset setup time t res 10 s oscillation stabilization wait time1 t wait1 2ms oscillation stabilization wait time2 t wait2 1ms sclk cycle time t kcy 1 mhz v pp setup time (to program command) t wa 1.8 ms program command data input wait time t wi 0.25 s program data command input wait time t wr 90 s v pp setup time (to verify command) t ra 1.8 ms verify command data output wait time t ri 5 s verify data command input wait time t re 0.25 s v pp setup time t oa 1.8 ms (to reset, increase, inhibit command) reset, increase, inhibit command t oi 0.25 s data (null) input wait time reset, increase, inhibit command t ot 0.25 s command input wait time
78 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds program memory access timing sclk si so v pp gnd v dd gnd v dd v pp do4 do3 do2 do1 do0 ci4 ci3 ci2 ci1 ci0 t res t wait1 t wait2 t wa, t ra, t oa t kcy t wi, t ri, t oi t wr, t re, t ot ci4 ci3 ci2 ci1 ci0
79 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 16. electrical specifications ( pd6p8b) (target) absolute maximum ratings (t a = +25 c) parameter symbol conditions rating unit power supply voltage v dd ?.3 to +5.0 v v pp ?.3 to +11.0 v input voltage v i k i/o0 -k i/o7 , k i0 -k i3 , s 0 , s 1 , s 2 ?.3 to v dd + 0.3 v output voltage v o ?.3 to v dd + 0.3 v output current, high i oh note rem peak value ?0 ma rms ?0 ma led peak value ?.5 ma rms ? ma per k i/o0 -k i/o7 pin peak value ?3.5 ma rms ? ma total for led and k i/o0 -k i/o7 peak value ?8 ma pins rms ?2 ma output current, low i ol note rem peak value 7.5 ma rms 5 ma led peak value 7.5 ma rms 5 ma operating ambient t a ?0 to +85 c temperature storage temperature t stg ?5 to +150 c note calculate the rms with: [rms] = [peak value] duty. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended power supply voltage range (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit power supply voltage v dd f x = 3.5 to 4.5 mhz 1.9 3.0 3.6 v
80 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) item symbol conditions min. typ. max. unit input voltage, high v ih1 k i/o0 -k i/o7 0.7v dd v dd v v ih2 k i0 -k i3 , s 0 , s 1 , s 2 0.65v dd v dd v input voltage, low v il1 k i/o0 -k i/o7 0 0.3v dd v v il2 k i0 -k i3 , s 0 , s 1 , s 2 0 0.15v dd v input leakage current, i lih1 k i0 -k i3 3 a high v i = v dd , pull-down resistor not incorporated i lih2 s 0 , s 1 , s 2 3 a v i = v dd , pull-down resistor not incorporated input leakage current, i lil1 k i0 -k i3 v i = 0 v 3 a low i lil2 k i/o0 -k i/o7 v i = 0 v 3 a i lil3 s 0 , s 1 , s 2 v i = 0 v 3 a output voltage, high v oh1 rem, led, k i/o0 -k i/o7 i oh = ?.3 ma 0.8v dd v output voltage, low v ol1 rem, led i ol = 0.3 ma 0.3 v v ol2 k i/o0 -k i/o7 i ol = 15 a 0.4 v output current, high i oh1 rem v dd = 3.0 v, v oh = 1.0 v 5 9 ma i oh2 k i/o0 -k i/o7 v dd = 3.0 v, v oh = 2.2 v ?.5 ? ma output current, low i ol1 k i/o0 -k i/o7 v dd = 3.0 v, v ol = 0.4 v 30 70 a v dd = 3.0 v, v ol = 2.2 v 100 220 a o n-chip pull-down resistor r 1 k i0 -k i3 , s 0 , s 1 , s 2 75 150 300 k ? r 2 k i/o0 -k i/o7 130 250 500 k ? data retention power v ddor in stop mode 1.2 3.6 v supply voltage ram retention detection v id 1.6 1.7 v voltage supply current i dd1 operation f x = 4.0 mhz, v dd = 3 v 10% 0.7 1.4 ma mode i dd2 halt mode f x = 4.0 mhz, v dd = 3 v 10% 0.65 1.3 ma i dd3 stop mode v dd = 3 v 10% 2.2 9.5 a v dd = 3 v 10%, t a = 25 c 2.2 3.5 a
81 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds ac characteristics (t a = ?0 to +85 c, v dd = 1.9 to 3.6 v) parameter symbol conditions min. typ. max. unit i nst ruc tio n execution time t cy 14 16 18.5 s k i0 -k i3 , s 0 , s 1 high-level t h 10 s width when releasing standby mode in halt mode 10 s in stop mode note s reset low-level width t rsl 10 s note 10 + 1024/f x + oscillation growth time remark t cy = 64/f x (f x : system clock oscillation frequency) poc circuit (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit poc detection voltage note v poc 1.8 1.9 v note refers to the voltage with which the poc circuit releases an internal reset. if v poc < v dd , the internal reset is released. from the time of v poc v dd until the internal reset takes effect, lag of up to 1 ms occurs. when the period of v poc v dd lasts less than 1 ms, the internal reset may not take effect. internal oscillator characteristics (t a = ?0 to +70 c, v dd = 2.0 to 3.6 v) parameter symbol conditions min. typ. max. unit oscillation frequency f x 3.92 4.0 4.08 mhz
82 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds prom programming mode dc programming characteristics (t a = 25 c, v dd = 3.0 0.3 v, v pp = 10.5 0.3 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 other than sclk 0.7v dd v dd v v ih2 sclk v dd ?0.5 v dd v input voltage, low v il1 other than sclk 0 0.3v dd v v il2 sclk 0 0.4 v input leakage current i li v in = v il or v ih 10 a output voltage, high v oh i oh = ? ma v dd ?1.0 v output voltage, low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 2ma v pp supply current i pp 0.3 ma cautions 1. keep v pp to within +11.0 v including overshoot. 2. apply v dd before v pp and turns it off after v pp . ac programming characteristics (t a = 25 c, v dd = 3.0 0.3 v, v pp = 10.5 0.3 v) parameter symbol conditions min. typ. max. unit reset setup time t res 10 s oscillation stabilization wait time1 t wait1 2ms oscillation stabilization wait time2 t wait2 1ms sclk cycle time t kcy 1 mhz v pp setup time (to program command) t wa 1.8 ms program command data input wait time t wi 0.25 s program data command input wait time t wr 90 s v pp setup time (to verify command) t ra 1.8 ms verify command data output wait time t ri 5 s verify data command input wait time t re 0.25 s v pp setup time t oa 1.8 ms (to reset, increase, inhibit command) reset, increase, inhibit command t oi 0.25 s data (null) input wait time reset, increase, inhibit command t ot 0.25 s command input wait time
83 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds program memory access timing sclk si so v pp gnd v dd gnd v dd v pp do4 do3 do2 do1 do0 ci4 ci3 ci2 ci1 ci0 t res t wait1 t wait2 t wa, t ra, t oa t kcy t wi, t ri, t oi t wr, t re, t ot ci4 ci3 ci2 ci1 ci0
84 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 17. characteristic curves (reference values) ( pd6p8) power supply current i dd [ma] power supply voltage v dd [v] i dd vs. v dd (fx = 4 mhz) (t a = 25 c) 1.5 2 3 2.5 3.6 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 operation mode halt mode 25 20 15 10 5 0 1 2 3 low-level output current i ol [ma] low-level output voltage v ol [v] i ol vs. v ol (rem, led) (t a = 25 c, v dd = 3.0 v) ? 20 ? 18 ? 16 ? 14 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 v dd v dd ? 1v dd ? 2v dd ? 3 high-level output current i oh [ma] high-level output voltage v oh [v] i oh vs. v oh (rem, led, k i/o ) (t a = 25 c, v dd = 3.0 v) 500 450 400 350 300 250 200 150 100 50 0123 low-level output current i ol [ a] low-level output voltage v ol [v] i ol vs. v ol (k i/o ) (t a = 25 c, v dd = 3.0 v)
85 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds note s 2 : set to stop mode release disabled k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 note k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 6 = 48 keys + mode select switch 18. application circuit example example of application to system ? remote-control transmitter (48 keys accommodated, mode selection switch accommodated)
86 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds ? remote-control transmitter (56 keys accommodated) note s 2 : set to stop mode release enabled k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 note k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 7 = 56 keys +
87 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds ? remote-control transmitter (56 keys accommodated, mode selection switch accommodated) data can be read from the k i/o0 to k i/o7 pins by connecting a pull-up resistor of approx. 50 k ? and a switch to these pins (which then become high level when the switch is on and low level when off). set the k i/o0 to k i/o7 pins to input mode at this time. reading data from these pins enables multiple output data to be obtained for the same key input. a pull-up resistor can be connected to any of pins k i/o0 to k i/o7 (the figure below shows an example of when a pull-up resistor is connected to the k i/o5 pin). note s 2 : set to stop mode release enabled k i/o6 k i/o7 s 0 s 1 /led rem v dd x out x in gnd s 2 note k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 7 = 56 keys mode selection switch v dd +
88 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 19. package drawing ns c dm m p l u t g f e b k j detail of lead end s 20 11 110 a h i item b c i l m n 20-pin plastic ssop (7.62 mm (300)) a k d e f g h j p t millimeters 0.65 (t.p.) 0.475 max. 0.13 0.5 6.1 0.2 0.10 6.65 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + ? 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note s20mc-65-5a4-2 each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 0.08 0.07 (unit:mm)
89 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 20. recommended soldering conditions the pd6p8, 6p8a, and 6p8b must be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 20-1. surface mounting soldering conditions pd6p8mc-5a4-a, 6p8amc-5a4-a, 6p8bmc-5a4-a: 20-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), ir60-207-3 count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 2 to 72 hours) wave soldering for details, contact an nec electronics sales representative. partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark products that have the part numbers suffixed by ?a?are lead-free products.
90 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds appendix a. development tools a prom programmer, program adapter, and an emulator are provided for the pd6p8, 6p8a, 6p8b. hardware ? prom programmer (af-9708 note , af-9709b note ) these prom programmers support the pd6p8, 6p8a, 6p8b. by connecting a program adapter to this prom programmer, the pd6p8, 6p8a, 6p8b can be programmed. note these are products of flash support group, inc. for details, consult flash support group, inc. (tel: +81-53-428-8380). ? program adapter (1) tef340-6p8 note this is used to program the pd6p8 in combination with the af-9708 or af-9709b. (2) tef340-6p8a note this is used to program the pD6P8A, 6p8b in combination with the af-9708 or af-9709b. note these are products of flash support group, inc. for details, consult flash support group, inc. (tel: +81-53-428-8380). ? emulator (eb-69 note , eb-69a note ) this is used to emulate the pd6p8, 6p8a, 6p8b. note these are products of naito densei machida mfg. co., ltd. for details, contact naito densei machida mfg. co., ltd. (+81-45-475-4191). software ? assembler (as6133 ver. 2.22 or later) this is a development tool for remote control transmitter software. part number list of as6133 host machine os supply medium part number pc-9800 series ms-dos tm (ver. 5.0 to ver. 6.2) 3.5-inch 2hd s5a13as6133 (cpu: 80386 or later) ibm pc/at tm compatible ms-dos (ver. 6.0 to ver. 6.22) 3.5-inch 2hc s7b13as6133 pc dos tm (ver. 6.1 to ver. 6.3) caution although ver.5.0 or later has a task swap function, this function cannot be used with this software.
91 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds appendix b. example of remote control transmission format (in the case of nec transmission format in command one-shot transmission mode) caution when using the nec transmission format, please apply for a custom code at nec electronics. (1) rem output waveform (from <2> on, the output is made only when the key is kept pressed) rem output 58.5 to 76.5 ms 108 ms 108 ms < 1 > < 2 > remark if the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (led) can be reduced by sending the reader code and the stop bit from the second time. (2) enlarged waveform of <1> rem output 13.5 ms leader code 9 ms 4.5 ms custom code 8 bits custom code 8 bits data code 8 bits data code 8 bits 27 ms 18 to 36 ms 58.5 to 76.5 ms stop bit 1 bit < 3 > (3) enlarged waveform of <3> rem output 9 ms 13.5 ms 0 4.5 ms 1100 2.25 ms 1.125 ms 0.56 ms (4) enlarged waveform of <2> rem output 9 ms 11.25 ms 2.25 ms 0.56 ms stop bit leader code
92 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds (5) carrier waveform (enlarged waveform of each code? high period) rem output 8.77 s 9 ms or 0.56 ms carrier frequency: 38 khz 26.3 s (6) bit array of each code c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 0 c 0 or c 8 c 1 c 1 or c 9 c 2 c 2 or c 10 c 3 c 3 or c 11 c 4 c 4 or c 12 c 5 c 5 or c 13 c 6 c 6 or c 14 c 7 c 7 or c 15 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 = = = = = = = = data code data code custom code custom code leader code caution to prevent malfunction with other systems when receiving data in the nec transmission format, not only fully decode (make sure to check data code as well) the total 32 bits of the 16-bit custom codes (custom code, custom code? and the 16-bit data codes (data code, data code) but also check to make sure that no signals are present.
93 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds 1 2 3 4 voltage application waveform at input pin w aveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
94 pd6p8, 6p8a, 6p8b data sheet u17848ej3v0ds the information in this document is current as of december, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibili ty for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. " standard": " special": " specific": ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. pc/at and pc dos are trademarks of international business machines corporation. caution: this product uses superflash ? technology licensed from silicon storage technology, inc.
pd6p8, 6p8a, 6p8b nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, j apan t el: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. t el: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china t el: 010-8235-1155 http://www.cn.necel.com/ shanghai branch room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai, p.r.china p.c:200120 t el:021-5888-5400 http://www.cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times square building, no. 4068 yi tian road, futian district, shenzhen, p .r.china p.c:518048 t el:0755-8282-9800 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong t el: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road t aipei, taiwan, r. o. c. t el: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 t el: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, y eoksam-dong, kangnam-ku, seoul, 135-080, korea t el: 02-558-3737 http://www.kr.necel.com/ f or further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany t el: 0211-65030 http://www.eu.necel.com/ hanover office p odbielskistrasse 166 b 30177 hannover t el: 0 511 33 40 2-0 munich office we r ner-eckert-strasse 9 81829 mnchen t el: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart t el: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. t el: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex fr ance t el: 01-3067-5800 sucursal en espa?a j uan esplandiu, 15 28007 madrid, spain t el: 091-504-2787 t yskland filial t? by centrum entrance s (7th floor) 18322 t?by, sweden t el: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy t el: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands t el: 040 265 40 10

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